PAN1326C Bluetooth Module
2 Overview
Product Specification Rev. 1.0
Page 16
•
The data position within a frame is also configurable in with 1 clock (bit) resolution and can
be set independently (relative to the edge of the Frame Sync signal) for each channel.
•
The Data_In and Data_Out bit order can be configured independently. For example;
Data_In can start with the MSB while Data_Out starts with LSB. Each channel is separately
configurable. The inverse bit order (that is, LSB first) is supported only for sample sizes up
to 24 bits.
•
It is not necessary for the data in and data out size to be the same length.
•
The Data_Out line is configured to ‘high-Z’ output between data words. Data_Out can also
be set for permanent high-Z, irrespective of data out. This allows the CC2564C to be a bus
slave in a multi-slave PCM environment. At power up, Data Out is configured as high-Z.
2.6.2.3 Frame Idle Period
The codec interface has the capability for frame idle periods, where the PCM clock can “take a
break” and become ‘0’ at the end of the PCM frame, after all data has been transferred.
The CC2564C supports frame idle periods both as master and slave of the PCM bus.
When CC2564C is the master of the interface, the frame idle period is configurable. There are
two configurable parameters:
•
Clk_Idle_Start
– Indicates the number of PCM clock cycles from the beginning of the frame
until the beginning of the idle period. After Clk_Idle_Start clock cycles, the clock will become
‘0’.
•
Clk_Idle_End
– Indicates the time from the beginning of the frame till the end of the idle
period. This time is given in multiples of PCM clock periods.
The delta between Clk_Idle_Start and Clk_Idle_End is the clock idle period.
For example, for PCM clock rate = 1 MHz, frame sync period = 10 kHz, Clk_Idle_Start = 60,
Clk_Idle_End = 90.
Between each two frame syncs there are 70 clock cycles (instead of 100). The clock idle period
starts 60 clock cycles after the beginning of the frame, and lasts 90
– 60 = 30 clock cycles. This
means that the idle period ends 100
– 90 = 10 clock cycles before the end of the frame. The
data transmission must end prior to the beginning of the idle period.
