SDD00026AEM
MN
6
6
2
7
8
5
T
B
U
C
Output current balance
in normal current mode
P
a
r
a
m
e
t
e
r
S
y
m
b
o
l
Conditions
Limits
Min
T
y
p
Max
U
n
i
t
Hi-Z
98
I
VFH
I
V
F
L
I
LKV
f
V
C
O
4
P
h
a
s
e
c
o
m
p
a
r
i
s
o
n
o
u
t
p
u
t
c
u
r
r
e
n
t
(
N
)
P
h
a
s
e
c
o
m
p
a
r
i
s
o
n
o
u
t
p
u
t
c
u
r
r
e
n
t
(
P
)
I
n
p
u
t
l
e
a
k
a
g
e
c
u
r
r
e
n
t
V
C
O
o
s
c
i
l
l
a
t
o
r
f
r
e
q
u
e
n
c
y
Variable pitch jitter-free mode
VCO frequency (for variable pitch
jitter-free) switching
＝×
0.5
Analog System Output Pin (3) VCOF (I
REF
pin is pulled up to AV
DD2
by a 47-k
Ω
resistor.)
Output current (N)
O
u
t
p
u
t
c
u
r
r
e
n
t
(
P
)
Output current balance
in normal current mode
P
h
a
s
e
c
o
m
p
a
r
i
s
o
n
o
u
t
p
u
t
c
u
r
r
e
n
t
(
N
)
Phase comparison
output current (P)
Input leakage current
P
C
K
o
s
c
i
l
l
a
t
o
r
f
r
e
q
u
e
n
c
y
I
D
S
H
I
D
S
L
I
D
S
B
L
I
P
F
H
I
P
F
L
I
LKP
I
P
L
B
L
f
VCO1
B
D
O
＝
L
,
T
r
a
c
k
i
n
g
O
N
-
s
t
a
t
e
D
S
L
F
＝
1
.
6
5
V
,
A
R
F
＝
3
.
3
V
B
D
O
＝
L
,
T
r
a
c
k
i
n
g
O
N
-
s
t
a
t
e
D
S
L
F
＝
1
.
6
5
V
,
A
R
F
＝
0
V
BDO
＝
L, Tracking ON-state
Normal current mode
B
D
O
＝
L
,
T
r
a
c
k
i
n
g
O
F
F
-
s
t
a
t
e
BDO
＝
L, Tracking OFF-state
B
D
O
＝
L
,
T
r
a
c
k
i
n
g
O
N
-
s
t
a
t
e
N
o
r
m
a
l
c
u
r
r
e
n
t
m
o
d
e
Normal- to 2x-speed jitter-free mode
VCO frequency (for PCK) switching
＝×
0.5
A
n
a
l
o
g
S
y
s
t
e
m
O
u
t
p
u
t
P
i
n
(
1
) D
S
L
F
(
I
R
E
F
p
i
n
i
s
p
u
l
l
e
d
u
p
t
o
A
V
D
D
2
b
y
a
4
7
-
k
Ω
r
e
s
i
s
t
o
r
.
)
Analog System Output Pin (2) PLLF (I
REF
pin is pulled up to AV
DD2
by a 47-k
Ω
resistor.)
C
1
8
C
1
9
C20
C
2
1
C
2
2
C
2
3
C24
C
2
5
C
2
6
C27
C28
C
2
9
Hi-Z
9
8
−
169
−
8.0
1
0
5
−
1
8
2
−
15.0
4.32
−
1
6
9
8
.
4
6
130
1
3
0
−
130
−
2
.
0
1
4
0
−
140
−
6
.
0
−
1
3
0
169
1
6
9
−
98
＋
4
.
0
1
8
2
−
1
0
5
±
1
＋
3
.
0
8.65
−
9
8
±
1
16.94
µ
A
µ
A
µ
A
µ
A
µ
A
µ
A
µ
A
µ
A
MHz
µ
A
µ
A
MHz
O
u
t
p
u
t
c
u
r
r
e
n
t
(
N
)
O
u
t
p
u
t
c
u
r
r
e
n
t
(
P
)
I
BAH
I
B
A
L
A
t
d
e
f
a
u
l
t
s
e
t
t
i
n
g
(
×
1
)
A
n
a
l
o
g
S
y
s
t
e
m
O
u
t
p
u
t
P
i
n
s
(
4
) T
B
A
L
,
F
B
A
L
(
I
R
E
F
p
i
n
i
s
p
u
l
l
e
d
u
p
t
o
A
V
D
D
2
b
y
a
4
7
-
k
Ω
r
e
s
i
s
t
o
r
.
)
C
3
0
C31
23
3
2
4
1
µ
A
µ
A
A
t
d
e
f
a
u
l
t
s
e
t
t
i
n
g
(
×
1
)
−
41
−
32
−
2
3
DV
DD1,2
＝
3.3 V, DV
SS1,2
＝
0 V
AV
DD1,2
＝
3.3 V, AV
SS1,2
＝
0 V
Ta
＝−
40
°
C to
＋
85
°
C
f
X1
＝
33.8688 MHz
71
Maintenance/
Discontinued
Maintenance/Discontinued includes following four Product lifecycle stage.
(planed maintenance type, maintenance type, planed discontinued typed, discontinued type)
