Panasonic MN34120PAJ Manual Download Page 68

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Confidential

Until : Indefinite

Specifications

MN34120PAJ

Total Page

Page

2015/10/01

Generalplus Technology Inc.

Enactment Revision

Panasonic Semiconductor Solutions Co., Ltd.

1.7.4.3 LVDS 1ch 6port / 2ch 3port Format Output

■

1ch 6port / 2ch 3port

Table 1.7.10 LVDS 1ch 6port / 2ch 3port format

m-1 line

VBLK (all"1")

m-5 line

m-4 line

m-3 line

m-2 line

･

0 line

1 line

2 line

3 line

4 line

･

P6n-3

･

P6n-3 P6n-2 P6n-1

P6n-7 P6n-6 P6n-5 P6n-4 P6n-3 P6n-2 P6n-1

P6n-7 P6n-6 P6n-5 P6n-4

P6n-3 P6n-2 P6n-1

P6n-7 P6n-6 P6n-5 P6n-4 P6n-3 P6n-2 P6n-1

P6n-7 P6n-6 P6n-5 P6n-4

P6n-2 P6n-1

P6n-7 P6n-6 P6n-5 P6n-4 P6n-3 P6n-2 P6n-1

P6n-7 P6n-6 P6n-5 P6n-4

P6n-3

P6n-6 P6n-5 P6n-4

P6n-3 P6n-2 P6n-1

P6n-7

P6n-7 P6n-6 P6n-5 P6n-4

P6n-3 P6n-2 P6n-1

P6n-2 P6n-1

P6n-7 P6n-6 P6n-5 P6n-4

EOL

HBLK

(all"1")

EOF

P6n-7 P6n-6 P6n-5 P6n-4 P6n-3 P6n-2 P6n-1

・

･

・

SOL

・

SOF

Table 1.7.11 Correspondence of ch/port and pin (1ch6port / 2ch3port format)

1ch 6port

2ch 3port

Port

Pin name

Port

Pin name

SDOD0



SDOD0



SDOD1



SDOD1



SDOD3



SDOD3



clk

SDOD5



clk

SDOD2



SDODA



SDODA



SDOD9



SDOD9



SDOD7



SDOD7



clk

SDOD8



Note : The character of P/M enters for “



”. These are regulations of all LVDS-terminal.

Summary of Contents for MN34120PAJ

Page 1: ...ct Standards Area Sensor MN34120PAJ Ver 1 02 Panasonic Semiconductor Solutions Co Ltd Established by Applied by Checked by Prepared by 2015 10 01 Generalplus Technology Inc Enactment Revision Panasonic Semiconductor Solutions Co Ltd ...

Page 2: ...each section are shown below Middle title Small title Text Note This is the Note Please read DUMMY Finding Desired Information This manual provides two methods for finding desired information quickly and easily 1 Consult the table of contents at the front of the manual to locate desired titles 2 Chapter names are located at the top outer corner of each page and section titles are located at the bo...

Page 3: ...vity 22 1 4 5 Sensitivity ratio 22 1 4 6 Average dark signal 23 1 4 7 OB level difference 23 1 4 8 Dark signal shading 24 1 4 9 Luminance shading 25 1 4 10 Color shading 25 1 5 Defect standard 26 1 5 1 Dark defects standard 26 1 5 2 Modulation defects standard 27 1 5 3 Adjacent defect judgment 28 1 5 4 Examples of pixel defect 29 1 6 Driving Condition 30 1 6 1 Serial IF 30 1 6 1 1 Send Write Timin...

Page 4: ... design 77 1 7 6 1 Exposure Time Control of Still Capture 77 1 7 6 2 Output timing chart in Still Capture 78 1 7 6 3 Cancel operation of Long Time Exposure in Still Mode 80 1 7 7 Sequence of Driving Mode transition Reference design 81 1 7 8 Signal output timing of Driving Mode transition Reference design 82 1 7 9 Sequence to change the extract position Reference design 82 1 7 10 Gain Control refer...

Page 5: ...Confidential Until Indefinite Specifications MN34120PAJ Total Page Page 96 3 2015 10 01 Generalplus Technology Inc Enactment Revision Panasonic Semiconductor Solutions Co Ltd Chapter1 Specifications 1 ...

Page 6: ...e Number of effective pixels 4660 H 3512 V 16 365 920 pixel Number of active pixels 4632 H 3488 V 16 156 416 pixel Total number of pixels 4804 H 3648 V 17 524 992 pixel Pixel size 1 335 H μm 1 335 V μm Number of pins 74 pins including pins of NC Actual imaging area dimensions active pixel area 6183 72 H μm 4656 48 V μm Color filter arrangement R G B primary color mosaic filters Power supply voltag...

Page 7: ...iguration The block configuration and pixel array of this product are described below Block configuration This product consists of pixel block high speed serial I F sub LVDS output PLL Timing generator TG Parallel column AD converter signal processing part and functional circuits of various kinds Serial IF SCS SCK SI TG HD VD PLL MCLK Output IF sub LVDS Signal processing Pixel Area Parallel A D co...

Page 8: ... R Gr R Gr R Gr R Gr R B Gb B Gb B Gb B Gb B Gb B Gb Gb B Gb B Gb B Gb B Gb B Gb Gr R Gr R Gr R Gr R Gr R Gr R R Gr R Gr R Gr R Gr R Gr R B Gb B Gb B Gb B Gb B Gb B Gb Gb B Gb B Gb B Gb B Gb B Gb Gr R Gr R Gr R Gr R Gr R Gr R R Gr R Gr R Gr R Gr R Gr R B Gb B Gb B Gb B Gb B Gb B Gb Gb B Gb B Gb B Gb B Gb B Gb Gr R Gr R Gr R Gr R Gr R Gr R R Gr R Gr R Gr R Gr R Gr R B Gb B Gb B Gb B Gb B Gb B Gb Gb...

Page 9: ... VD Vertical standard pulse I O IO Vertical standard pulse I O Slave mode input Master mode output 14 B9 SCK Serial clock I 15 C1 SDOD1M LVDS output port01 data O 16 C2 SDOD1P LVDS output port01 data O 17 C3 SDOD4P LVDS output port03 data O Zdiff 100Ω under 1 18 C4 VRES Resistance for internal voltage O open 19 C5 TM Digital test terminal I Connect GND 20 C6 PSV Power save terminal I Low Power sav...

Page 10: ... is arranged between GND 59 H10 VDD33 Digital 3 3V power supply P Decoupling capacity 2 2μF is arranged between GND 60 H11 VCHP2 Down converter IO Connect 1 0μF bypath capacitance between AGND 1 61 J3 SDODAP LVDS output port10 data O Zdiff 100Ω under 1 62 J4 GNDL Digital 1 8V GND G 63 J5 VDD18L Digtal 1 8V power supply P Decoupling capacity 2 2μF is arranged between GNDL 64 J6 VDD Digtal 1 2V powe...

Page 11: ...5 G2 46 G3 47 G9 48 G10 49 G11 50 H1 51 H2 52 H3 53 H4 54 H5 55 H6 56 H7 57 H8 58 H9 59 H10 60 H11 61 J3 62 J4 63 J5 64 J6 65 J7 66 J8 67 J9 68 K3 69 K4 70 K5 71 K6 72 K7 73 K8 74 K9 VRES SDOD4P SDOD1P SDOD1M AVDDP AVDDR VCHP1 AVDDPL AGNDR AGNDP AGNDPL AGNDC AGNDP AGNDC HD VD SCK CAPD1 SI MCLK VDD SCS PSV VDD TESTIO SDOD3M SDOD0P SDOD2P GND SDOD0M SDOD2M GND SDOD4M TM SDOD3P SDOD5P SDOD6P SDOD7P S...

Page 12: ...er limit Min Typ Max AVDD AVDDP AVDDR AVDDPL AVDDSD V 0 3 4 0 3 15 3 3 3 45 AVDDC V 0 3 2 5 1 7 1 8 1 9 DVDD VDD33 V 0 3 4 0 3 15 3 3 3 45 VDD18 VDD18 VDD18L V 0 3 2 5 1 7 1 8 1 9 VDD12 VDD V 0 3 1 7 1 1 1 2 1 3 VCHP1 V Internal Internal VCHP2 V Internal Internal VCHP3 V Internal Internal AGND AGNDP AGNDC AGNDR AGNDPL V GND 0 DGND GND GNDL Note The absolute maximum ratings are the limit values app...

Page 13: ...it mode in the Industrial Devices Company mounting environment Temperature Conditions Table 1 1 6 Temperature Conditions Parameter Unit Lower limit Typ Upper limit Remarks Operating temperature 10 25 83 1 Performance assurance temperature 0 25 60 2 Storage temperature 30 25 85 1 1 Operating temperature and storage temperature are defined by the temperature around the sensor Operating temperature s...

Page 14: ... Low level VIL 0 VDD18 0 2 V Input leak current ILI VI VDD18 or GND 5 A Input LVCMOS level Schmitt PSV SCK SCS Input threshold voltage VT VDD18 1 62V 1 98V 1 05 VDD18 0 9 V VT VDD18 0 1 0 75 Input leak current ILI VI VDD18 or GND 5 A Input Output LVCMOS level HD VD Input voltage High level VIH VDD18 0 8 VDD18 V Input voltage Low level VIL 0 VDD18 0 2 V Output voltage High level VOH IO 3 2mA VDD18 ...

Page 15: ...nous signal HD Horizontal synchronous signal VD pulse specifications falling edge standard 50 Tvdh Vcycle VD rising edge standard 50 Figure 1 2 2 1 1 Definition of VD pulse input timing specifications HD pulse specifications falling edge standard HD 50 Thdh Hcycle rising edge standard 50 Figure 1 2 2 1 2 Definition of HD pulse input timing specifications Table 1 2 2 AC characteristics of VD and HD...

Page 16: ...ng Figure is described by the rising edge standard Figure 1 2 2 1 3 Definition of HD VD input timing specifications Table 1 2 3 AC characteristics of HD VD input signal Reference design Symbol Min Typ Max Unit Thdly 5 ns HCYCLE 10T MCLK MCLK timing specifications TH 50 TL MCLK Figure 1 2 2 1 4 Definition of MCLK input timing specifications Table 1 2 4 AC characteristics of MCLK input signal Refere...

Page 17: ...ge VCM 0 8 0 9 1 0 V Amplitude range of output differential voltage VOD 100 150 200 mV Terminal resistance value Zdiff 98 100 102 Ω external resistance 1 VCM variation VCM 25 25 mV VOD variation VOD 25 25 mV Duty ratio TH TL 45 50 55 SDOD P SDOD M 5nH 4pF 5nH 4pF Zdiff Figure 1 2 2 2 1 Maximum output load of LVDS output SDO VCM VOD SDOD P SDOD M Figure 1 2 2 2 2 Definition of output voltage of LVD...

Page 18: ...lows Table 1 2 6 AC Characteristics of LVDS Output Signal Parameter Symbol Min Typ Max Unit Remarks Internal operating frequency 648 MHz Set up time Tlvdssh 420 ps Hold time Tlvdshd 420 ps Figure 1 2 2 2 5 Definition of AC Characteristics of LVDS Output Signal Note The figure of 0 9 or the character of A enters for and it becomes specifications of all LVDS pins Tlvdssh SDOC P SDOC M SDOD P SDOD M ...

Page 19: ...Saturated output 1 Gr 1 4 3 Saturated illuminance R Gr Gb B signal output 1599 LSB Gb 1599 LSB R 1599 LSB B 1599 LSB Sensitivity Gr 1 4 4 Standard illuminance R Gr Gb B signal output 1810 2453 LSB Gb 1802 2444 LSB R 702 1054 LSB B 630 996 LSB Sensitivity ratios R Gr 1 4 5 Standard illuminance R Gr Gb B signal output 0 32 0 58 ratio B Gb 0 28 0 52 ratio Average dark signal 1 4 6 60 C light shielded...

Page 20: ...0A 0000 0000 0000 0E07 0274 02DE 03FC 03EB 03E2 03A1 0800 0000 012 0000 0C07 0405 0000 000C 03A0 216C 0C07 0000 000F 0000 000F 000F 0056 0000 0800 013 0000 0000 0004 0194 02FC 02FC 02F3 02F3 02C3 02C3 0000 0062 01E1 003C 2900 0055 014 0053 018E 0000 0060 019E 0320 02FC 02FC 0004 019E 000F 001D 0320 0010 0500 0018 015 1107 0030 1805 1106 005F 018E 005F 018E 0005 3032 0030 0000 3002 1003 1B60 0032 0...

Page 21: ...Inc Enactment Revision Panasonic Semiconductor Solutions Co Ltd 1 3 3 Spectral Characteristics Spectral characteristics are described below Reference value 0 00 0 10 0 20 0 30 0 40 0 50 0 60 0 70 0 80 0 90 1 00 400 450 500 550 600 650 700 750 800 Wavelength nm Relative Output Figure 1 3 1 Spectral Characteristics ...

Page 22: ...d illuminance The standard illuminance is defined as using a Halogen bulb color temperature 3200 K inserting an IR cut filter CM500S t 2 5mm in the optical path and achieving an illuminance of 6 51 lx at the sensor surface The illuminance of the sensor surface with above conditions is the standard illuminance Lens aperture F8 equivalent Definition of the saturated illuminance Saturated illuminance...

Page 23: ...s In addition OB area in Figure 1 4 1 is also tested 4712 OB area 76 88 7 32 23 3488 3590 3512 62 4632 18 14 Measurement area Figure 1 4 1 Measurement area of dark defects 1 4 2 Modulation defects Measure the sensor output signal of a measurement area shown in the Figure 1 4 2 below in the standard illuminance at the standard imaging state and calculate the modulation defects from the following fo...

Page 24: ... Measurement area Figure 1 4 3 Measurement area of saturated output 1 4 4 Sensitivity Measure the sensor output signal of a measurement area shown in the Figure 1 4 4 below in the standard illuminance at the standard imaging state and calculate the sensitivity from the following formula Sensitivity LSB average output for individual color channel in the measurement area Also Gr Gb sensitivity ratio...

Page 25: ...ement area of the average dark signal 1 4 7 OB level difference Measure the sensor output signal of a measurement area shown in the Figure 1 4 6 below in the light shielded state at the standard imaging state Determine the average of the active pixel area EAave and the average of the OB area OBave and substitute the values into the following formula OB level difference LSB EAave OBave Determine th...

Page 26: ... Max Dk k 0 to 10 4712 76 308 15 blocks 88 3512 D0 max Ai0 min Aj0 i j 0 to 14 D1 max Ai1 min Aj1 i j 0 to 14 317 3590 3487 7 32 24 29 D10 max Ai10 min Aj10 i j 0 to 14 4620 15 A 0 0 A 1 0 A 2 0 A 13 0 A 14 0 A 0 10 A 0 9 A 0 1 A 0 2 A 14 10 A 13 10 Figure 1 4 7 Measurement area of Dark signal shading Horizontal dark signal shading 2 Vertical signal shading Measure the sensor output signal in the ...

Page 27: ... blocks 88 3512 317 3590 3487 7 32 24 29 4620 15 OB area A 0 0 A 1 0 A 2 0 A 13 0 A 14 0 A 0 10 A 0 9 A 0 1 A 0 2 A 14 10 A 13 10 Measurement area Figure 1 4 9 Measurement area of luminance shading 1 4 10 Color shading Measure the sensor output signal of a measurement area shown in the Figure 1 4 9 below in the standard illuminance at the standard imaging state Measure the color average value for ...

Page 28: ...umber of single defects and adjacent defects 3 See 1 5 3 Adjacent defect judgment of page 28 for the counting definition of adjacent defects Dark defects standard Single defects Defect level LSB Allowance count X 74 5 LSB Not count 74 5 LSB X 2620 367 6 LSB X nDW 1 Count the single defects which level is over 74 5 LSB 2 Not count the single defects which level is under or equal 74 5 LSB 3 See 1 4 ...

Page 29: ... adjacent defects 4 See 1 4 2 Modulation defects of page 21 for the area of counting defects Modulation defects standard Defect contrast Modulation white black single defect counts Modulation white black adjacent defect counts X 20 nB1 0 20 X 10 nB2 Not count 10 X 10 Not count 10 X 20 nW1 20 X nW2 0 1 Count the single defects which contrast is over 10 2 Not count the single defects which contrast ...

Page 30: ...Gb B Gb B Gb B Gb B Gb B R Gr R Gr R Gr R Gr R Gr R Gr R Gr R Gr Gb B Gb B Gb B Gb B Gb B Gb B Gb B Gb B Gb pixel B pixel R Gr R Gr R Gr R Gr R Gr R Gr R Gr R Gr Gb B Gb B Gb B Gb B Gb B Gb B Gb B Gb B R Gr R Gr R Gr R Gr R Gr R Gr R Gr R Gr Gb B Gb B Gb B Gb B Gb B Gb B Gb B Gb B R Gr R Gr R Gr R Gr R Gr R Gr R Gr R Gr Gb B Gb B Gb B Gb B Gb B Gb B Gb B Gb B R Gr R Gr R Gr R Gr R Gr R Gr R Gr R G...

Page 31: ... R Gr R Gb B Gb B Gb B Gb R Gr R Gr R Gr R Gb B Gb B Gb B Gb R Gr R Gr R Gr R Gb B Gb B Gb B Gb R Gr R Gr R Gr R Gb B Gb B Gb B Gb R Gr R Gr R Gr R Gb B Gb B Gb B Gb R Gr R Gr R Gr R Gb B Gb B Gb B Gb R Gr R Gr R Gr R Gb B Gb B Gb B Gb R Gr R Gr R Gr R Gb B Gb B Gb B Gb R Gr R Gr R Gr R Gb B Gb B Gb B Gb R Gr R Gr R Gr R Gb B Gb B Gb B Gb R Gr R Gr R Gr R Gb B Gb B Gb B Gb R Gr R Gr R Gr R Gb B Gb...

Page 32: ...yte 2byte 3byte 4byte 1cycle 4bytes Figure 1 6 1 Definition of Send Write Timing SCS Low Packet transmission of register write Packets are transmitted by 1cycle 4byte except for consecutive writing mode Refer to Consecutive Writing Mode write only about consecutive writing mode When transmission is broken up set SCS High Set SCK clock 2T or more and try transmission again The data format at transm...

Page 33: ... dividing frequency setting The range in the register address is as follows 0x0000 0x0011 PSV SCS SCK SI tRST_p tSCS0 tSCW tSST tSHD tSCS1 tSCS2 D9 D14 D15 D7 Low A0 D1 D8 A1 A2 A13 A14 D0 Figure 1 6 1 1 1 Definition of Send Write Timing for PLLREG Register Table 1 6 2 AC Characteristics of Send Write Timing for PLLREG Register Reference design Parameter Min Typ Max Unit Remarks tRST_p 30 ns From ...

Page 34: ... tSCS0 tSCW tSST tSHD tSCS1 tSCS2 D8 D15 Low D9 D14 A0 A1 A2 A13 A14 D0 D1 D7 Figure 1 6 1 1 2 Definition of Send timing for excluding PLLREG register Write Table 1 6 3 AC Characteristics of Send Timing for excluding PLLREG Register Reference design Parameter Min Typ Max Unit Remarks tRST 60 ns From the internal reset release r_clkrst High to SCS Low tSCS0 30 ns From SCS Low to the SCK input tSCS1...

Page 35: ... Command Data 16bit Write PSV Data 7 0 Lower 8bit Data 15 8 Upper 8bit Register Address 14 0 D14 D15 D1 Figure 1 6 1 1 3 Operation Timing after Receipt of Write Command Consecutive Writing Mode write only Addresses to write are automatically incremented in this mode during SCS Low r_clkrst tSCSR 0 nsec SCS SCK SI 1byte 2byte 3byte 4byte 3byte 4byte 3byte 4byte Address n data data data Data of addr...

Page 36: ...r an access to the internal register with serial IF has limitation Basically an access in the vertical blanking period is recommended Please confirm 1 7 2 1 Output timing for vertical blanking period V_BACK Register writing period V_BACK VD HD LVDS Internal VD Data output Blanking Data output Figure 1 6 2 1 Timing of register writing Note The timing chart since this chapter is described by VD fall...

Page 37: ...l VD Data output Blanking Register writing Reflection timing Type1 Reflection timing Type2 Register setting update latch Data output Blanking Data output Blanking Figure 1 6 2 2 Update timing for Register Setting Note Please refer to the Register Specifications for the Update timing of each register Name Update timing VD Update at internal vertical synchronizing signal Update at the active edge of...

Page 38: ...ollowing figure for the power on sequence of each syste 1 2V 3 3V 0V 1 8V VDD18 Power supply 80 VDD33 Power supply 80 VDD12 Power supply 80 T1 0V T2 0V Figure 1 6 3 1 1 Definition of Power On Sequence Table 1 6 6 AC Characteristics of Power On Sequence Reference design Power on sequence Symbol Min Typ Max Unit VDD18 power supply VDD12 power supply T1 0 ms VDD12 power supply VDD33 power supply T2 0...

Page 39: ...I F 7 Wait for stabilizing the oscillation of PLL Wait until PLL output clock is stabilized The register other than PLLREG can not be written normally when the waiting time for PLL oscillation stability is not enough 8 Cancel the reset of internal clock division Set the register by the 3 wire serial I F The clock can be supplied to the internal logic by canceling the reset of the internal clock di...

Page 40: ...stability is not enough Wait over 1μsec Power ON Row circuit power save release Register setting PLL and circuit of dividing frequency register setting Other PLLREG register setting PLL oscillation stability waiting Tpll Up Down converter circuit Reset release Register setting Up Down converter circuit Stability waiting Tvchp TG reset release Register setting Taking picture beginning Registers oth...

Page 41: ...S enable time Tpulvds PSV release waiting Tpsv Up Down converter circuit Stability waiting Tvchp Don t care high low Don t care high low circuit of dividing frequency and Up Down converter circuit reset release BLK Blanking Data output Figure 1 6 3 2 2 Timing chart of Initialization Table 1 6 8 Initialization timing Parameter Symbol Min Typ Max Unit PSV release waiting Tpsv 10T MCLK MCLK input wai...

Page 42: ... the electronic shutter register to 4 or more when 5 times or more HD can not be input after canceling TG reset in the initialize sequence The return sequence of Power Save described in 1 6 3 3 should be done same operation VD HD Internal signal TG reset register Don t care high low Don t care high low Electronic shutter register change Value 4 TG reset release VD HD Input Figure 1 6 3 2 3 When 5 ...

Page 43: ...ister or the PSV pin Table 1 6 9 List of power save mode Mode Control Status Pin Power save register 0x000E 3 0 PSV Normal Operation H 4 b0011 Normal Operation Power save 1 H 4 b0010 The internal logic PLL circuit Up converter Down converter is operated Power save 2 H 4 b0000 The internal logic Up converter Down converter is operated Power save 3 1 H 4 b0001 Power save The internal logic stops Pow...

Page 44: ...y Up Down converter circuit stability waiting unnecessary unnecessary necessary Table 1 6 12 Characteristics of power save mode Power save mode Power save 1 Power save 2 Power save 3 1 Power save 3 2 Standby power 1 150 mA 75 mA 5 mA Return time 2 1 ms 2 1 ms Stability waiting of PLL oscillation 33 ms Stability waiting of PLL oscillation and Up Down converter circuit 1 The condition of above value...

Page 45: ...ollows 1 Power save register 0x000E 3 0 writing 4 b0011 4 b0000 TG reset register 0x0000 8 writing H L Up Down converter circuit register 0x0005 2 1 writing 2 b00 2 b10 CKG reset register 0x0000 4 writing H L Power save shift waiting Hcycle External pin PSV High MCLK SCK SI SCS VD Don t care High Low HD Don t care High Low LVDS Internal signal Register Power save register CKG Reset register TG Res...

Page 46: ...ing waiting Hcycle Shift sequence from normal to power save 3 2 is as follows 1 TG reset register 0x0000 8 writing H L CKG reset register 0x0000 4 writing H L PSV pin polarity change timing waiting Hcycle 2 PSV pin H L External pin PSV High MCLK SCK SI SCS VD HD LVDS Internal signal Register Power save register CKG Reset register TG Reset register Hcycle or more Tpdlvds 1 2 Power save mode3 1 High...

Page 47: ...x000E 3 0 writing The power save is canceled by the rising edge of the SCS pin TG reset register 0x0000 8 writing L H HD input beginning VD input timing waiting wait over 5HD input 2 VD HD Input External pin PSV High MCLK SCK SI SCS VD HD LVDS Internal signal Register Power save register CKG Reset register High TG Reset register Tpulvds HD input Don t care High Low Don t care High Low Blanking 4 b...

Page 48: ...CS pin PLL oscillation stability waiting 2 CKG reset register 0x0000 4 writing H L Up Down converter circuit register 0x0005 2 1 writing 2 b10 2 b00 TG reset register 0x0000 8 writing L H HD input beginning VD input timing waiting wait over 5HD input 3 VD HD Input External pin PSV High MCLK SCK SI SCS VD HD LVDS Internal signal Register Power save register CKG Reset register TG Reset register HD i...

Page 49: ...G register writing PLL oscillation stability waiting 4 CKG reset register 0x0000 4 writing L H 5 Registers other than PLLREG register writing Up Down converter circuit stability waiting 6 TG reset register 0x0000 8 writing L H HD input beginning VD input timing waiting wait over 5HD input 7 VD HD Input External pin PSV MCLK SCK SI SCS VD HD LVDS Internal signal Register Power save register CKG Res...

Page 50: ...ng 4 CKG reset register 0x0000 4 writing L H 5 Registers other than PLLREG register writing Up Down converter circuit stability waiting 6 TG reset register 0x0000 8 writing L H HD input beginning VD input timing waiting wait over 5HD input 7 VD HD Input External pin PSV MCLK SCK SI SCS VD HD LVDS Internal signal Register Power save register CKG Reset register TG Reset register 10T MCLK Tpll HD inp...

Page 51: ...8 12 4712 3590 918 3620 0 51 2 Full scan 10bit 22 32 8 10 4712 3590 666 3632 0 52 3 V2 2mix H2mix 29 97 4 12 2356 1804 792 2275 6 91 4 V2 2mix_c H2mix 59 94 50 6 12 2364 1366 650 750 1386 1440 0 24 1 03 5 V2 2mix_c H2mix 59 94 50 6 10 2388 1366 630 750 1430 1440 0 75 1 03 6 V3 3mix H3mix 26 89 4 12 1572 1208 1638 1226 0 55 7 V2 3mix H3mix 59 94 4 10 1572 1212 630 1430 2 54 8 V2 3mix_c H3mix 59 94 ...

Page 52: ...S H_TR_E Figure 1 7 2 1 Pixel format in each driving mode Table 1 7 2 Pixel format in each driving mode 1 No Mode Pixel composition 1 Full scan 12bit 1ch8port12bit 2ch4port12bit Horizontal pixel composition Total H_S1 HOB H_S2 TR_S active TR_E H_E 4712 2 42 4 14 4632 14 4 Vertical pixel composition Total V_T TR_T active TR_B V_B 3590 76 12 3488 12 2 2 Full scan 10bit 1ch8port10bit 2ch4port10bit Ho...

Page 53: ...S active TR_E H_E 2364 2 20 2 8 2314 8 10 Vertical pixel composition Total V_T TR_T active TR_B V_B 1366 46 6 1304 6 4 5 V2 2mix_c H2mix 1ch6port10bit 2ch3port10bit Horizontal pixel composition Total H_S1 HOB H_S2 TR_S active TR_E H_E 2388 2 42 4 8 2314 8 10 Vertical pixel composition Total V_T TR_T active TR_B V_B 1366 46 6 1304 6 4 6 V3 3mix H3mix 1ch4port12bit 2ch2port12bit Horizontal pixel com...

Page 54: ... H_E 1572 1 13 6 5 1543 4 0 Vertical pixel composition Total V_T TR_T active TR_B V_B 544 38 4 496 4 2 10 V3 13mix H3mix 1ch4port10bit 2ch2port10bit Horizontal pixel composition Total H_S1 HOB H_S2 TR_S active TR_E H_E 1572 1 13 6 5 1543 4 0 Vertical pixel composition Total V_T TR_T active TR_B V_B 310 32 4 268 4 2 11 Full scan 5 division output 1ch8port10bit 2ch4port10bit Horizontal pixel composi...

Page 55: ... Output timing The output timing chart is shown in Figure 1 7 2 1 1 Output timing from HD and VD in each Driving Mode are shown in Table 1 7 5 EOF V_BACK EOL SOL EOL SOL EOL SOL EOL SOL EOL EOL Pixel array EOL SOL EOL SOL EOL SOL EOL SOL EOL V_FRONT Vcycle V_PIX SOF SOL SOL SOL HD Hcycle VD H_FRONT H_PIX H_BACK Figure 1 7 2 1 1 Output timing chart from HD and VD and number of CYCLE ...

Page 56: ... 470 4 V2 2mix_c H2mix 12 650 750 1386 1440 550 α 2412 938 α 1538 α 1 1366 19 73 5 V2 2mix_c H2mix 10 630 750 1430 1440 507 α 2030 1243 α 1963 α 1 1366 63 73 6 V3 3mix H3mix 12 1638 1226 586 α 2406 6836 α 1 1208 17 7 V2 3mix H3mix 10 630 1430 507 α 2005 1268 α 1 1212 217 8 V2 3mix_c H3mix 12 630 720 1430 1500 586 α 2406 788 α 1328 α 1 924 505 575 9 V3 7mix H3mix 12 630 1260 1260 715 715 1430 586 α...

Page 57: ...wer save cancel timing and the power save shift timing can be set by the unit of Hcycle Please refer to the MN34120PA register specifications in details VD HD LVDS Power save Off LVDS Hi z Hi z Power save On Tpdlvds Tpulvds Blanking V_FRONT V_PIX V_BACK EOL BLK SOL n 1 Line BLK SOL 1Line LVDS Power save cancel timing LVDS Power save shift timing Blanking SOF 0Line EOL BLK EOF Blanking EOL BLK SOL ...

Page 58: ...PIX is sequentially output Afterwards it is period of Horizontal Back Blanking H_BACK Each Blanking period and record pixel depends on driving mode Please refer to the output timing table Table 1 7 5 in details HD LVDS Blanking Blanking SOL Valid Data EOL HCYCLE H_FRONT H_PIX H_BACK Figure 1 7 2 1 3 Data output timing chart H cycle Note The period of Horizontal Front Blanking H_FRONT changes becau...

Page 59: ...epending on the driving mode The output array is decided by combining the horizontal and vertical mixing It explains reading pixel format of pixel mixture mode as follows V2 2mix H2mix Mode No 3 No 4 No 5 Gr 0_0 R 0_1 B 1_0 Gb 1_1 Gr 0_2 R 0_3 B 1_2 Gb 1_3 Gr 2_0 R 2_1 B 3_0 Gb 3_1 Gr 2_2 R 2_3 B 3_2 Gb 3_3 R Gb R Gb Gr B Gr B Gb B Gb B Gb B R Gr R Gr R Gr Gr R B Gb Gr Gr0_0 Gr2_0 Gr0_2 Gr2_2 R R0...

Page 60: ..._6 R 2_7 B 3_6 Gb 3_7 Gr 4_0 R 4_1 B 5_0 Gb 5_1 Gr 4_2 R 4_3 B 5_2 Gb 5_3 Gr 4_4 R 4_5 B 5_4 Gb 5_5 Gr 4_6 R 4_7 B 5_6 Gb 5_7 Gr 6_0 R 6_1 B 7_0 Gb 7_1 Gr 6_2 R 6_3 B 7_2 Gb 7_3 Gr 6_4 R 6_5 B 7_4 Gb 7_5 Gr 6_6 R 6_7 B 7_6 Gb 7_7 B Gb B Gb B Gb B Gb Gb B R Gb R Gb R Gb R Gb R Gr R Gr R Gr R Gr R Gr Gr B Gr B Gr B Gr B Gr Gr0_0 Gr2_0 Gr4_0 Gr0_2 Gr2_2 Gr4_2 Gr0_4 Gr2_4 Gr4_4 R R0_3 R2_3 R4_3 R0_5 R...

Page 61: ...b 3_3 Gr 2_4 R 2_5 B 3_4 Gb 3_5 Gr 2_6 R 2_7 B 3_6 Gb 3_7 Gr 4_0 R 4_1 B 5_0 Gb 5_1 Gr 4_2 R 4_3 B 5_2 Gb 5_3 Gr 4_4 R 4_5 B 5_4 Gb 5_5 Gr 4_6 R 4_7 B 5_6 Gb 5_7 Gr 6_0 R 6_1 B 7_0 Gb 7_1 Gr 6_2 R 6_3 B 7_2 Gb 7_3 Gr 6_4 R 6_5 B 7_4 Gb 7_5 Gr 6_6 R 6_7 B 7_6 Gb 7_7 B Gb R Gb R Gb R Gb R Gb R Gb B Gb B Gb B Gb B Gb R Gb R Gb R Gb R Gb Gr B Gr B Gr B Gr B Gr Gr0_0 Gr4_0 Gr0_2 Gr4_2 Gr0_4 Gr4_4 R R0_...

Page 62: ...5_6 Gb 5_7 Gr 6_0 R 6_1 B 7_0 Gb 7_1 Gr 6_2 R 6_3 B 7_2 Gb 7_3 Gr 6_4 R 6_5 B 7_4 Gb 7_5 Gr 6_6 R 6_7 B 7_6 Gb 7_7 Gr 8_0 R 8_1 B 9_0 Gb 9_1 Gr 8_2 R 8_3 B 9_2 Gb 9_3 Gr 8_4 R 8_5 B 9_4 Gb 9_5 Gr 8_6 R 8_7 B 9_6 Gb 9_7 Gr 10_0 R 10_1 Gr 10_2 R 10_3 Gr 10_4 R 10_5 Gr 10_6 R 10_7 B 11_0 Gb 11_1 B 11_2 Gb 11_3 B 11_4 Gb 11_5 B 11_6 Gb 11_7 B Gb B Gb B Gb B Gb Gb B Gb B Gb B Gb B Gb B Gb B Gb B Gr R G...

Page 63: ...4_1 B 15_0 Gb 15_1 Gr 14_2 R 14_3 B 15_2 Gb 15_3 Gr 14_4 R 14_5 B 15_4 Gb 15_5 Gr 14_6 R 14_7 B 15_6 Gb 15_7 Gr 16_0 R 16_1 B 17_0 Gb 17_1 Gr 16_2 R 16_3 B 17_2 Gb 17_3 Gr 16_4 R 16_5 B 17_4 Gb 17_5 Gr 16_6 R 16_7 B 17_6 Gb 17_7 Gr 18_0 R 18_1 B 19_0 Gb 19_1 Gr 18_2 R 18_3 B 19_2 Gb 19_3 Gr 18_4 R 18_5 B 19_4 Gb 19_5 Gr 18_6 R 18_7 B 19_6 Gb 19_7 Gr 20_0 R 20_1 B 21_0 Gb 21_1 Gr 20_2 R 20_3 B 21_2...

Page 64: ...The output format is different depending on the driving mode and the output bit length changes The recognition code is output before and after record pixel output The description of output format symbol is shown in Table as follows Table 1 7 7 Description of output format symbol Recognition code Symbol Word length Description Px Output bit Pixel output SOF Output bit 4 Recognition Code for frame s...

Page 65: ...6 P8n 5 P8n 4 P8n 3 P8n 2 P8n 1 P8n 7 P8n 6 P8n 5 P8n 4 P8n 1 P8n 7 P8n 6 P8n 5 P8n 4 P8n 3 P8n 2 P8n 1 P8n 5 P8n 4 P8n 3 P8n 2 P8n 7 P8n 6 P8n 5 P8n 4 P8n 3 P8n 2 P8n 1 P8n 7 P8n 6 VBLK all 1 EOL HBLK all 1 EOF P4 P5 P6 P4 P5 P6 P0 P1 P2 P3 P0 P1 P2 P3 P4 P5 P6 P0 P1 P2 P3 P0 P1 P2 P3 P4 P5 P6 P0 P1 P2 P3 P4 P5 P6 P4 P5 P6 P0 P1 P2 P3 P4 P5 P6 P0 P1 P2 P3 P4 P5 P6 P0 P1 P2 P3 SOL P0 P1 P2 P3 P4 P...

Page 66: ...000h FFFh 000h 000h SOF SOL 000h 000h FFFh FFFh FFFh 000h 000h 002h 12 h000 12 h000 12 h01D SOF 000h P8n 9 11 0 P8n 1 11 0 12 hFFF P23 10 12 h000 12 h000 12 h019 12 hFFF 12 h000 12 h000 12 h01C P7 11 0 P15 11 0 P23 11 0 P8n 11 11 0 P8n 3 11 0 12 hFFF 12 h000 12 h000 12 h015 12 hFFF 12 h000 12 h000 12 h018 P5 11 0 P13 11 0 P21 11 0 P8n 13 11 0 P8n 5 11 0 12 hFFF 12 h000 12 h000 12 h011 12 hFFF 12 h...

Page 67: ... SOL EOL EOF EOL EOF SOF SOL EOL EOF SOF SOL EOL EOF EOL EOF SOF SOL EOL EOF SOF SOL EOL EOF SOF SOL 10 h000 10 h000 10 h01D SOF 3FFh 000h 000h 002h 3FFh 000h P8n 9 9 0 P8n 1 9 0 10 h3FF 10 h000 10 h000 10 h019 10 h3FF 10 h000 10 h000 10 h01C P7 9 0 P15 9 0 P23 9 0 P8n 11 9 0 P8n 3 9 0 10 h3FF 10 h000 10 h000 10 h015 10 h3FF 10 h000 10 h000 10 h018 P5 9 0 P13 9 0 P21 9 0 P8n 13 9 0 P8n 5 9 0 10 h3...

Page 68: ...P6n 3 P6n 2 P6n 1 P6n 7 P6n 6 P6n 5 P6n 4 P6n 3 P6n 6 P6n 5 P6n 4 P6n 3 P6n 2 P6n 1 P6n 7 P6n 7 P6n 6 P6n 5 P6n 4 P6n 3 P6n 2 P6n 1 P6n 2 P6n 1 P6n 7 P6n 6 P6n 5 P6n 4 EOL HBLK all 1 EOF P6n 7 P6n 6 P6n 5 P6n 4 P6n 3 P6n 2 P6n 1 P4 P5 P6 P0 P1 P2 P3 P4 P5 P6 P0 P1 P2 P3 P4 P5 P6 P0 P1 P2 P3 P0 P1 P2 P3 P4 P5 P6 P0 P1 P2 P3 P4 P5 P6 P4 P5 P6 P0 P1 P2 P3 P4 P5 P6 P0 P1 P2 P3 P4 P5 P6 P0 P1 P2 P3 SOL...

Page 69: ...00 12 h005 12 hFFF 12 h000 12 h000 12 h008 P4 11 0 P10 11 0 P16 11 0 P6n 8 11 0 P6n 2 11 0 12 hFFF 12 h000 12 h000 12 h009 12 hFFF 12 h000 12 h000 12 h010 P1 11 0 P7 11 0 P13 11 0 P6n 11 11 0 P6n 5 11 0 12 hFFF 12 h000 12 h000 12 h011 12 hFFF 12 h000 12 h000 12 h014 P3 11 0 P9 11 0 P15 11 0 P6n 9 11 0 P6n 3 11 0 12 hFFF 12 h000 12 h000 12 h015 12 hFFF 12 h000 12 h000 12 h018 P5 11 0 P11 11 0 P17 1...

Page 70: ... P6n 8 9 0 P6n 2 9 0 10 h3FF 10 h000 10 h000 10 h009 10 h3FF 10 h000 10 h000 10 h010 P1 9 0 P7 9 0 P13 9 0 P6n 11 9 0 P6n 5 9 0 10 h3FF 10 h000 10 h000 10 h011 10 h3FF 10 h000 10 h000 10 h014 P3 9 0 P9 9 0 P15 9 0 P6n 9 9 0 P6n 3 9 0 10 h3FF 10 h000 10 h000 10 h015 10 h3FF 10 h000 10 h000 10 h018 P5 9 0 P11 9 0 P17 9 0 10 h019 SOF SOL EOL P6n 7 9 0 P6n 1 9 0 10 h3FF 10 h000 P17 7 P17 6 SOL EOL EOF...

Page 71: ...n 2 P4n 1 P4n 7 P0 P1 P2 P3 P4n 1 P0 P1 P4n 7 P4n 6 P4n 5 P4n 3 P4n 6 P4n 5 P4n 4 P4n 4 P4n 3 P4n 2 P4n 1 P0 P1 P2 P3 P4 P5 P6 P4n 7 P0 P1 P2 P3 P4n 4 P4n 3 P4n 2 P4n 1 P4n 7 P4n 6 P4n 5 P4n 3 P4n 2 P4n 1 P0 P1 P2 P3 P4 P5 P6 P4n 7 P4n 6 P4n 5 P4n 4 P4 P5 P6 P0 P1 P2 P3 P4n 4 P4n 3 P4n 2 P4n 1 P4n 7 P4n 6 P4n 5 P4n 3 P4n 2 P4n 1 P0 P1 P2 P3 P4 P5 P6 P4n 7 P4n 6 P4n 5 P4n 4 P4 P5 P6 P0 P1 P2 P3 P4n...

Page 72: ... h000 12 h000 12 h001 12 hFFF 12 h000 12 h000 12 h004 P2 11 0 P6 11 0 P10 11 0 P4n 7 11 0 P4n 2 11 0 12 hFFF 12 h000 P4n 6 11 0 12 h000 12 h005 12 hFFF 12 h000 12 h000 12 h010 P1 11 0 P5 11 0 P9 11 0 12 h000 12 h014 P3 11 0 P7 11 0 12 h000 P11 8 port 12 h011 P11 11 0 P4n 5 11 0 P4n 3 11 0 12 hFFF 12 h000 SOF SOL EOL 12 h015 SOF SOL EOL P4n 1 11 0 12 hFFF 12 h000 SOF SOL EOL EOF 000h 002h FFFh 000h...

Page 73: ...t P3 0 P7 9 P7 8 P7 7 P7 6 P7 5 P7 4 P7 3 P11 6 P11 5 P7 2 P7 1 P7 0 P11 9 P4n 8 9 0 P11 8 P4n 4 9 0 10 h3FF P4n 6 9 0 P4n 2 9 0 10 h3FF 10 h000 P0 9 0 P4 9 0 P8 9 0 10 h000 10 h000 10 h001 10 h3FF 10 h000 10 h000 10 h004 P2 9 0 P6 9 0 P10 9 0 10 h000 10 h000 10 h005 10 h3FF 10 h000 10 h000 10 h010 P1 9 0 P5 9 0 P9 9 0 P4n 7 9 0 P4n 3 9 0 10 h3FF 10 h000 10 h000 10 h011 10 h3FF 10 h000 10 h000 10 ...

Page 74: ... P4 P5 P6 P2n 7 P2n 6 P2n 5 P2n 4 P2n 3 P2n 2 P2n 1 P0 P1 P2 P3 P4 P5 P6 P2n 7 P2n 6 P2n 5 P2n 4 P2n 3 P2n 2 P2n 1 P0 P1 P2 P3 P4 P5 P6 P2n 7 P2n 6 P2n 5 P2n 4 P2n 3 P2n 2 P2n 1 P0 P1 P2 P3 P2n 5 P2n 4 P4 P5 P6 P2n 1 P0 P1 P2 P3 P4 P5 P6 P2n 7 P2n 6 P2n 7 P2n 6 P2n 5 P0 P1 P2 P3 P4 P5 P6 EOF P2n 7 P2n 6 P2n 5 P2n 4 P2n 3 P2n 2 P2n 1 P2n 4 P2n 3 P2n 2 P2n 1 P2n 3 P2n 2 VBLK all 1 HBLK all 1 EOL SOL...

Page 75: ...FF 12 h000 12 h000 12 h000 P0 11 0 P2 11 0 P4 11 0 P2n 4 11 0 P2n 2 11 0 12 hFFF 12 h000 12 h000 12 h001 12 hFFF 12 h000 12 h000 12 h010 P1 11 0 P3 11 0 P5 11 0 P2n 3 11 0 P2n 1 11 0 12 hFFF 12 h000 12 h000 12 h011 port10 ch2 port0 P1 3 P1 2 P1 1 P1 0 P3 11 P3 10 P3 9 P3 8 P5 10 P5 9 P5 8 P3 3 P3 2 P3 1 P3 0 Name Code 12bit 4 CLK_M P5 11 P3 7 P3 6 P3 5 P3 4 Name Code 12bit 4 EOL EOF FFFh 000h SOF ...

Page 76: ...de 3FFh 000h 000h 003h 000h 000h 013h 3FFh 000h 000h 011h 3FFh 3FFh 000h 000h 010h 3FFh 000h 000h 012h 3FFh 000h 000h 001h 000h 002h 3FFh 000h 000h 000h SOF SOL EOL EOF P5 4 Name Code 10bit 4 Name Code 10bit 4 P5 8 P5 6 P5 5 P3 2 P3 1 P5 7 10 h000 10 h011 P1 3 P1 2 P1 1 P1 0 P3 9 P3 8 P3 7 P3 6 P2n 3 9 0 P2n 1 9 0 10 h3FF P3 0 P5 9 P3 5 P3 4 P3 3 10 h000 10 h000 10 h001 10 h3FF 10 h000 10 h000 10 ...

Page 77: ...ter setting register Exposure time is from internal electronic shutter start signal to next internal VD Please refer to the MN34120PA register specifications in details VD HD LVDS Internal VD electronic shutter start signal internal Electronic shutter setting register writing Exposure time Electronic shutter setting update latch Electronic shutter setting update data Exposure time of change Data o...

Page 78: ...me exposure register Please refer to the MN34120PA register specifications for details VD HD LVDS Internal VD electronic shutter start signal internal Long exposure setting register writing Long exposure setting update latch Long exposure setting update data Blanking Exposure time Blanking Data output Blanking Data output Figure 1 7 5 2 1 Long time exposure mode timing Note The update data after t...

Page 79: ... time over 1VD The number of frames is controlled by the long time exposure setting register Method No 2 The number of long time exposure frames is controlled by trigger output of register Exposure time is controlled as follows Exposure time within 1VD The rising edge of reset signal for Still mode is controlled by the electronic shutter setting register Exposure time over 1VD After waiting approp...

Page 80: ...Blanking Invalid Data OPEN CLOSE OPEN Still instruction LVDS Blanking The position can be changed by electronic shutter register Figure 1 7 6 2 1 Timing chart of Still exposure control Method 1 Within 1VD exposure Still operation Method 1 Over 1VD exposure The number of long time exposure frames is set by the register External pin VD HD Internal signal Internal VD Still reset signal High period 5H...

Page 81: ...ut Invalid Data OPEN CLOSE OPEN Blanking The position can be changed by electronic shutter register Figure 1 7 6 2 3 Timing chart of Still exposure control Using tg_rst2 Within 1VD exposure Still operation Method 2 Over 1VD exposure The number of long time exposure frames is controlled by trigger output of register Output trigger of Still data 0x00 L setting period Update at internal VD after stil...

Page 82: ... time can be output The still data is output after Long Time Exposure Setting 1 VD set in the long time exposure cancel instruction When the setting of Long Time Exposure Setting 1 is 0VD the still data is output from the next frame of long time exposure cancel instruction External pin VD HD LVDS Dummy output invalid Internal signal Internal VD Still reset signal Reference Mechanical shutter Expos...

Page 83: ...e biginning TG reset register L H address 0x0000 data 0x0173 HD VD input Initial sequence flow Mode change TG reset register H L address 0x0000 data 0x0073 No Yes HD input Over 5times HD Wait over 1 Hcycle Change number of ports or bits No Yes Change the setting data address 0x0004 Change the setting data 1 and set the TG setting register 1 address 0x0004 address 0x0006 address 0x0020 address 0x00...

Page 84: ...ut BLK Data output Blanking Data output Driving Mode transition register writing TG reset register writing Driving Mode update data Figure 1 7 8 Timing chart of Driving Mode transition 1 7 9 Sequence to change the extract position Reference design In the extract output mode No 11 FULL SCAN 5 division output the extract position can be changed by writing the register Flag of mode change and the ext...

Page 85: ... refer to the MN34120PA Register specifications in detail Analog Gain Analog gain can be set by analog gain register 0x0061 Analog gain is shown by the next expression Analog Gain 0 09375 analog gain register setting data 256 dB Analog Gain variable range 12 0 dB 23 9 dB Useful range of register dec 128 511 Digital Gain Digital gain can be set by digital gain register 0x0062 Digital gain is shown ...

Page 86: ...D0M SDOD1P SDOD1M SDOD4P SDOD4M SDOD6P SDOD6M SDOD9P SDOD9M SDODAP SDODAM LVDS Output VCHP1 VCHP2 VD input output HD input output CAPD1 SDOD3P SDOD3M SDOD7P SDOD7M AGNDR AGNDPL AGNDC GNDL VDD18L AVDDPL TESTIO open 4 7μF BIASO open TM 2 2μF AGNDP 1 8V power supply Digital 3 3V power supply Digital 1 8V power supply Analog 2 2μF 2 2μF 2 2μF ch1 port00 ch1 port01 ch1 port02 ch1 port03 ch1 port13 ch1 ...

Page 87: ...OD3P SDOD3M SDOD6P SDOD6M SDOD8P SDOD8M SDOD9P SDOD9M LVDS Output VCHP1 VCHP2 VD input output HD input output CAPD1 SDOD2P SDOD2M SDOD7P SDOD7M AGNDR AGNDPL AGNDC GNDL VDD18L AVDDPL TESTIO open 4 7μF BIASO open TM 2 2μF AGNDP 1 8V power supply Digital 3 3V power supply Digital 1 8V power supply Analog 2 2μF 2 2μF 2 2μF ch1 port0 ch1 port1 ch1 clock ch1 port3 ch2 port4 ch2 port3 ch2 clock ch2 port2...

Page 88: ... land TL at BIASO is a test terminal for the management analysis Please install the TL pin when there is allowable space The grounded capacitor for CAPD1 must be used temperature property B rank 10 more over The grounded capacitor for VCHP1 CHP2 VCHP3 must be used temperature property B rank 10 more over Please use temperature property B rank 10 more over for the decoupling capacitor of the power ...

Page 89: ...al Until Indefinite Specifications MN34120PAJ Total Page Page 96 87 2015 10 01 Generalplus Technology Inc Enactment Revision Panasonic Semiconductor Solutions Co Ltd 1 8 Package 1 8 1 Dimensions H V 0 32 0 01 mm ...

Page 90: ...ifications The product type date code and original country of products are shown on the back of the package Specifications of product number place of manufacture and code number 1 Product number 2 ID number A123456 78901B3 34120PA Indication item Indication contents Description 1 Product type 34120PA MN34120PA series 2 ID number 14 characters UTAC UTAC Manufacturing Services Singapore Pte Ltd ...

Page 91: ... devices are stacked with a sixth empty tray at the top and taped at 3 points together 3 1 Tray external view Material Conductive PPE Tray name HD A102116 Tray dimensions 300 0 152 5 mm t 7 62 mm Products are placed in the tray with the package A1pin aligned in the same direction with the tray notch 3 2 Packing figure showing how the six trays are stored Insert the trays into a aluminum pack and t...

Page 92: ...rted in the packing case One shock absorbing pad is inserted between the lower and upper levels If one aluminum pack one spacer is inserted in the upper level 3 The packing case lid is sealed with precision component packing tape 4 Product name C 3 labels are placed in clearly visible positions on the sides and top of the box 5 A D label is attached at the stipulated location on the side of the bo...

Page 93: ... fiber clothing staff should always wear work clothes and uniforms made from antistatic materials Also staff should wear conductive footwear 4 When handling MOS sensors do not use nylon gloves only use cotton gloves Also staffs who handle MOS sensor must be grounded The most common technique is to wear a grounding bracelet on the wrist when working with MOS sensors For safety reasons always insert...

Page 94: ...ipulated in the device standard exceeded 2 Do not apply power with the MOS sensor pins connected incorrectly That could result in source drain reversals or the protection transistors being forward biased The resulting large currents could destroy the aluminum interconnects on the chip 3 Do not use a power supply whose transient voltage levels exceed the maximum ratings 4 In order to prevent latch ...

Page 95: ...ring Limit temperature Manual soldering Possible damage due to higher temperature than the limit MOS device part 245 C 190 C Degradation of on chip filter and lens Glass surface 245 C 190 C Degradation of adhesive Glass sealing area 245 C 225 C Degradation of adhesive How to measure temperature Reflow 4 Cautions for re soldering a Please be careful when MOS device that was removed once is re solde...

Page 96: ...ee environment We recommend using an ionized air blower to remove contamination that adheres due to static electricity If an air blower is used all the MOS sensor pins must be grounded as an antistatic measure 3 If oil or other contamination that cannot be removed by the above methods adheres to the glass surface use a clean cotton swab or lens cleaning paper dampened with a small amount of isopro...

Page 97: ...n a radiation static electricity and ferromagnetic field environment 6 Since such as chlorine in tap water may cause to rust the leads please use once boiled water in the humidifier 7 Note in after opening an anti moisture packing Silica gel packed with After anti moisture packing is opened please store MOS sensor in the environment of Ta 5 30 C and RH 70 or less Since adhesive joint between the p...

Page 98: ...oltage wave forms driving timing and so on coincide with the conditions described in this Specifications 2 This guarantee does not apply if either of the following cases applies 1 White defects after shipping caused by cosmic rays As time passes MOS sensor is subject to the sudden occurrence of white defects due to cosmic rays 2 When returning a MOS sensor a fault report form is not included or th...

Page 99: ...Panasonic Semiconductor Solutions Co Ltd 1 Kotari yakemachi Nagaokakyo City Kyoto 617 8520 Japan Tel 075 951 8151 ...

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