PAN1322
Application Note
13
Revision 1.2, 2013-12-18
Design Guide
2
Interfaces
2.1
UART Interface
The UART interface is the main communication interface between the host and eUniStone. For the SPP
application, communication between the host and the eUniStone is through AT commands over the
UART interface.
The interface consists of four UART signals for the AT interface and two GPIOs for additional low
power mode control, as shown in
Figure 2. UART Interface
2.1.1
Low Power Mode Control
The use of low power mode (LPM) control is optional. If not used, P0.14 shall be tied to VDDUART.
The low power mode protocol for eUniStone is based on hardware signaling only. No AT commands or
responses are required for the low power mode protocol. The two GPIOs are used to tell the other
device (host or controller) when it may enter low power mode, when it should wake up and when it
cannot transmit because the other device is in low power mode.
To allow the eUniStone to enter low power mode, the host sets pin P0.14 low. When eUniStone is
ready, it will also allow the host to enter LPM by setting P0.0 low. Before entering LPM, the host shall
set UART CTS of eUniStone high. Before entering LPM, eUniStone will set its own UART RTS high.
UARTTXD
UARTRXD
UARTTXD
UARTRXD
UARTRTS
UARTCTS
UARTCTS
UARTRTS
Host
eUniStone
P 0 . 0
P 0 . 14
BT _ LPM
_ IN
BT _ LPM _ OUT