Panasonic EB-GD93, Technical Manual

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HERCULES
MCUK001001G8 Section 7 Issue 1
Technical Guide – 29 – Revision 0
7.5. Interrupt Handler
The ARM CPU has two interrupts. FIQ is a Fast non-maskable interrupt and IRQ is a standard maskable interrupt.
HERCULES has 16 interrupt sources. The interrupt handler assigns priorities to these interrupts and routes them to either the
FIQ or IRQ inputs of the ARM CPU. Additionally, the interrupt handler controls waking up of the CPU on receiving an unmasked
interrupt, if the CPU is in sleep mode.
The FIQ interrupt is reserved for the power supply fail priority interrupt. This interrupt comes from OMEGA chip INT1.
The interrupt priorities are programmed through interrupt level registers. The interrupt has 23 registers:
Interrupt Level Assignments
Interrupt Source Description Interrupt detection
IRQ0 Watchdog Timer INT Edge sensitive
IRQ1 Timer 1 INT Edge sensitive
IRQ2 Timer 2 INT Edge sensitive
IRQ3 OMEGA fast interrupt Low Level sensitive (FIQ)
IRQ4 TPU frame INT Edge sensitive
IRQ5 TPU page INT Edge sensitive
IRQ6 SIM INT Edge sensitive
IRQ7 UART modem / IRDA INT Low Level sensitive
IRQ8 Keyboard INT Low Level sensitive
IRQ9 RTC periodical timer INT Edge sensitive
IRQ10 RTC Alarm / ULPD / I2C INT Low Level sensitive
IRQ11 ULPD gauge timer Edge sensitive
IRQ12 External INT Low Level sensitive
IRQ13 SPI INT Edge sensitive
IRQ14 DMA INT Low Level sensitive
IRQ15 API INT Edge sensitive
$FFFF:FA00 Interrupt pending register Read only / Reset
$FFFF:FA02 Mask interrupt register Read / Write
$FFFF:FA04 IRQ source register Read only
$FFFF:FA06 FIQ source register Read only
$FFFF:FA08 IRQ source register (binary) Read only
$FFFF:FA0A FIQ source register (binary) Read only
$FFFF:FA0C Control Register Read / Write
$FFFF:FA0E IRQ0 interrupt register Read / Write
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$FFFF:FA2C IRQ15 interrupt level register Read / Write