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7.2.4 Interrupt Handler
The ARM CPU has 2 interrupts. FIQ is a Fast non maskable interrupt and IRQ is a standard maskable interrupt.
GEMINI has 11 interrupt sources, The interrupt handler assigns priorities to these interrupts and routes them to
either the FIQ or IRQ inputs of the ARM CPU. Additionally the interrupt handler controls waking up of the CPU on
receiving an unmasked interrupt, if the CPU is in sleep mode.
For G600 the FIQ interrupt is reserved for the power supply fail priority interrupt.
Interrupt level assignments
Interrupt source
Description
Interrupt detection
IRQ_TIM1
Buzzer timer
Edge sensitive
IRQ_TIM2
operating system timer
Edge sensitive
IRQ_API
DSP Interface interrupt
Edge sensitive
IRQ_EXT
Power supply fail interrupt
Level sensitive
IRQ_USART
UART Interrupt
Level sensitive
IRQ_ARMIO
Keypad Interrupt
Low for 1 clk period
IRQ_FRAME
Frame Interrupt
Edge sensitive
IRQ_PAGE
Page Interrupt
Edge sensitive
IRQ_TIM_GSM
Edge sensitive
IRQ_TSP
Timed serial port Interrupt
Edge sensitive
IRQ_SIM
SIM Interrupt
Level sensitive
IRQ_F_USART
Fast interrupt from USART
Level sensitive
IRQ_RSS
Radio subsystem interrupt
Edge sensitive
7.2.5 General Purpose I/O
The general purpose I/O includes keypad scanning, 2 PWM ports and 16 I/O general purpose I/O lines. The
general purpose I/O lines are multiplexed onto other functions; if I/O is selected the other function is unavailable.
I/O pin Assignments
Signal
GEMINI Pin
Use
Signal
IO (0) /nLCDCS
117
nLCDCS
IO (1) /RXE
116
STAY_ALIVE
H = PSU kept on
L = PSU off
IO (2) /TXE
115
VEGA_PWRDWN
L = VEGA powered up
H = VEGA powered down
IO (3) /DTR
114
HF_ON
L = Hands free Off
H = Hands free On
IO (4) /DSR
110
RADIO_MUTE
L = Radio Mute Off
H = Radio Mute On
MCUK980101G8
Section 7
Issue 1
Technical Guide
7 - 3
Revision 0
GEMINI