Panasonic AG-DV2500P, Service Manual

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4-5
* Voltage figures shown are target values for software control, and may differ somewhat from the actual voltage. Please regard them
as rough estimates.
Table 4.2.4 Voltage and Mechanism Position Comparison
Mode sensor voltage Mechanism position Mode
0.273 ± 0.03 V UNLOAD END position NO CASSETTE MODE
1.314 ± 0.03 V BRAKE position FF/REW Modes in which tension band is used as brake for stopping
1.691 ± 0.03 V FAST position FF/REW MODE
2.111 ± 0.03 V STOP position STAND-BY OFF
2.716 ± 0.03 V SEARCH position PLAY/REC/SEARCH/STAND-BY ON
4.3 SYSTEM CONTROL
4.3.1 Outline
The control system is comprised of the SYSCON CPU (IC2001) on the MAIN board assembly, and the VCR (MSD) CPU (IC302) on the
DV/CPU board assembly. Both of these are connected by a bus called the MS_BUS, and communicate via serial data transfer.
4.3.2 Communication specifications
(1) SYSCON CPU turns the CS from “L” “H” and communication begins.
(2) SYSCON CPU confirms that the BUSY terminal is “L”, and transmits data at CLOCK1.68MHz as well as receives data from the
VCR (MSD) CPU.
(3) VCR (MSD) CPU also sends and receives data in accordance with CLK. However, if it is not yet ready for communication it sets the
BUSY terminal to “H” and notifies the SYSCON CPU.
(4) When the BUSY terminal is “H”, SYS CPU skips the current communication and waits until the next block (400 µs later) to see if
it is “L” and then starts communication.
(5) After 25 Bytes are communicated, CS is set to “L” and communication ends.
4.3.3 Communication timing
In synchronization with internal reference sync, communication takes place once every 16.6 ms (NTSC) or 20 ms (PAL). Byte interval
is 400 µs. When necessary the contents of the communication are changed at the 1st2nd field.
Communication type Clock synchronous serial communication
Communication speed 1.68 Mbps
Data length 8bit x 25
Bit order MSB head
Clock generation source SYS CPU
Data direction Full duplex
Table 4.3.1 MS_BUS Communication Settings
Fig. 4.3.1 MS BUS Connection
SYS
CPU
VTR
(MSD)
CPU
CS(H)
CLOCK
DATA1
DATA2
BUSY(H)
4.2.7 Mode sensor
The AG-DV2500’s mode sensor adopts the variable resistor method (MECHA board VR1) which uses changes in resistance to detect
the position of the mechanism. The changed voltage, brought about by changes in the resistance value due to mechanism position, is
sent to DV/CPU IC302 to made to the A/D conversion. The mechanism position is judged by this.