OPTO 22 PCI-AC51, User Manual

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STROBE DURATION
PCI-AC51 User’s Guide
42
Strobe Duration
Legacy Pamux documentation indicates that the on-time specification of the read and write strobes
were 2,000 ns. Through the lifecycle of Pamux hardware, this time was increased to 2,700ns (brain
and AC28’s with a Lattice chip).
When S5 is on, the PCI-AC51 maintains the last AC28 (Rev K) timing specification, 2,700 ns.
Switching to the 3,300 ns setting may improve long cable issues.
High and Low Latency Modes
The amount of idle time between Pamux bus cycles has never been specified. Historic Pamux
hardware assumed that there was adequate software delay time between each bank access. Recent
PCs are capable of performing back-to-back bus cycles with nearly no delay (as little as 60 ns).
The PCI-AC51 (state machine version 2) enforces idle time between bus cycles. When S6 is on (high
latency mode), 3,600 ns of idle time is added between each bus cycle. This means the busy bit may
be busy for as much as 7,700 ns. The additional delay time is required for many B6 analog brains.
These brains are software driven and need the additional time to properly operate.
In some cases of digital only systems (systems that contain only B4, SNAP-B4, or B5 brains), S6 may
be turned off (low latency mode) if the additional latency is undesirable.
Performing Pamux Operations
Issuing Pamux Reset
The PCI-AC51 provides a level oriented reset control feature.
1. Assert the Pamux Reset by writing a value to the Reset Control Register (BAR1, offset 0x00),
bit 0. A zero sets the Pamux reset level to low. A one sets the Pamux reset level to high.
2. Poll the status register and inspect the state of Reset Busy. Wait for the bit to negate (return to
zero). The Reset Busy enforces a 150 ms delay interval, the recommended reset duration for all
Pamux hardware. Digital-only brains may reset with a much shorter interval.
3. Negate the Pamux Reset signal by writing a complementary value to bit 0 of the Reset Control
Register.
NOTE: Reset is asynchronous to all Pamux operations. Reset may be asserted while the Pamux bus cycle is
in operation (Status Register Busy Bit is asserted). If a Pamux read was in progress, the result is uncertain. If
a write is in progress, the reset must be asserted well after the Pamux bus cycle is completed. If the reset is
negated before the end of the current Pamux write, the written result is uncertain.
NOTE: A substantial reset period is required for analog or mixed brains. Typically, a Pamux analog brain will
reset if the Reset is asserted for 150 ms. The Reset Busy bit in the Reset Status Register provides a 150 ms
busy indication. Note this is simply an indicator. Additional changes to the reset state will immediately
appear on the Pamux Reset signal and the 150 ms timer is reset upon each write to the Reset Control
Register.