OPTO 22 PCI-AC51, User Manual

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APPENDIX D: PCI-AC51 TECHNICAL REFERENCE
PCI-AC51 User’s Guide
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Register Description
Reset Status Register (0x00)
The Reset Status Register reports the reset state (Reset Level,
bit 0) and the status of a 150 ms timer (Reset Busy, bit 7). The timer provides the application a way to
ensure a minimum reset duration for all Pamux brains. The timer is reset (and the Reset Busy Bit set
to 1) when register 0x00 (Reset Control Register) is written. When the duration expires, the Reset
Busy Bit is set to 0.
Reset Control Register (0x00)
Bit 0 drives the reset signal on the Pamux bus. Writing a 1
asserts the reset signal to the “high level.” Writing a 0 asserts the reset signal to the “low level.”
Bank Address Register (0x01)
The Pamux address for the next Pamux read/write cycle is
stored in this register. This register must not be modified while the Busy Bit of the Status Register is
set to 1.
Data Register (0x02)
Do not access this register while a Pamux operation is in progress.
Writing : The data to be written in the next Pamux write cycle should be stored in this register before
the Pamux write cycle is finished.
Reading : After the Pamux read cycle is complete, this register holds the data that was read from the
Pamux brain.
Start Read Register (0x03)
A read initiates a Pamux read bus cycle. Reading from this register
initiates a Pamux read. The bank Address Register must be configured before reading from this
register. A value of 0xAB is always returned in this register and can be ignored. The data read from
the Pamux brain is returned in the Data Register. Do not access this register while a Pamux operation
is in progress.
Start Write Register (0x03)
Writing to this register initiates a Pamux write cycle. The Bank
Address Register and the Data Register must be configured before writing to this register. Do not
access this register while a Pamux operation is in progress.
Status Register (0x04)
This register contains the Busy bit (busy = 1), to indicate if a Pamux bus
cycle is in progress. The ID bits hold the value of the last brain communicated with. These bits are
valid only after the Busy bit is 0. The Write Status bit is 1 if the current or last Pamux bus cycle was a
Pamux write cycle. The Read Status bit is 1 if the current or last Pamux bus cycle was a Pamux read.
Switch Register (0x05)
Provides state of the switches on the PCI-AC51. Custom driver
applications may use S1 through S4 in any desired fashion. S5 and S6 may be verified for proper
hardware settings.
Version Register (0x06)
Returns the version of the state machine architecture.