Onkyo DV-SP302, Service Manual

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DV-SP302
IC BLOCK DIAGRAM/ TERMINAL DESCRIPTION
IC10 : ES6629 VIDEO PROCESSOR-(4)
TWS
116
O Audio transmit frame sync output.
SEL_PLL2 I System and DSCK output clock frequency selection is made at the rising edge of
RESET#. The matrix below lists the available clock frequencies and their
respective PLL bit settings. Strapped to VCC or ground via 4.7-k resistor; read-
only during reset.
TSD0
117
O Audio transmit serial data port 0.
SEL_PLL0 I Refer to the description and matrix for SEL_PLL2 pin 116.
TSD1
118
O Audio transmit serial data port 1.
SEL_PLL1 I Refer to the description and matrix for SEL_PLL2 pin 116.
TSD[2:3] 120, 121 O Audio transmit serial data ports 2 and 3.
MCLK 122 I/O Audio master clock for audio DAC.
TBCK 123 O Audio transmit bit clock.
SPD_DOBM
124
O S/PDIF output.
SEL_PLL3 I Clock source select. Strapped to VCC or ground via 4.7-k resistor; read only
during reset.
SPDIF_IN 125 I S/PDIF input; (5V tolerant input).
WBLCLK 128 O DVD-RAM wobble detector circuit clock source to preamp.
WBL 129 O DVD-RAM wobble output.
LG 130 O DVD-RAM land/groove flag.
IP2 131 I DVD-RAM header position index 2.
IP1 132 I DVD-RAM header position index 1.
FLAG[3:0] 133:136 O To monitor servo status.
TEXI 139 I High-speed tracking error input.
TESTAD 140 I Test AD input.
SBAD 141 I Sub-beam addition input signal.
FEI 142 I Focus input error signal.
Table 1 ES6629 Pin Description (Continued)
Names Pin Numbers I/O Definitions
SEL_PLL2 SEL_PLL1 SEL_PLL0 Clock Type (MHz)
0 0 0 CLK .5
0 0 1 CLK 5.0
0 1 0 Bypass
0 1 1 CLK 4.0
1 0 0 CLK 4.25
1 0 1 CLK 4.75
1 1 0 CLK 5.5
1 1 1 CLK 6.0
SEL_PLL3 Clock Source
0 Crystal oscillator
1 CLK input