Onkyo DV-SP302, Service Manual

Page: 50 / 69

DV-SP302
IC BLOCK DIAGRAM/ TERMINAL DESCRIPTION
IC91 : uPD16311 FL Driver-(3)
PIN FUNCTION
Pin No. Symbol Pin name Description
DIN
DOUT
STB
CLK
OSD
Seg1/KS1 to
Seg12/KS12
Grid1 to Grid6
Seg13/Grid16 to
Seg20/Grid9
LED1 to LED6
Key1 to Key4
SW1 to SW4
VDD
VSS
VEE
IC
Data input
Inputs serial data at rising edge of shift clock,
starting from lower bit.
Outputs serial data at falling edge of shift clock, starting from
lower bit. This is N-ch open-drain output pin.
Initializes serial interface at rising or falling edge to make
uPD16311 waiting for reception of command. Data input
after STB has fallen is processed as command. While command
data is processed, current processing is stopped, and serial interface
is initializes. While STB is high, CLK is ignored.
Reads serial data at rising edge, and outputs data at falling edge.
Connect resistor for determining oscillation frequency to this pin.
Segment output pins (Dual function as key source).
Grid output pins.
Tease pins are selectable for segment or grid output.
CMOS output. +20 mA max..
Data input to these pins is latched at end of display cycle.
These pins constitute 4-bit general-purpose input port.
5 V = 10 %
connect this pin to GND of system.
VDD - 35 V max.
Be sure to leave this pin open (this pin is at VDD level).
Data output
Strobe
Clock input
Oscillator pin
High-voltage output
(segment)
High-voltage output (Grid)
High-voltage output
(segment/ grid)
LED output
Key data input
switch input
Logic power
Logic ground
Pull-down level
Internally connection
6
5
9
8
52
15 to 26
44 to 37
27 to 32
35 to 36
50 to 46
10 to 13
1 to 4
14, 33, 45
51
34
7