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AN-6094 
 

© 2012 Fairchild Semiconductor Corporation 

 

www.fairchildsemi.com 

Rev. 1.0.0  •  9/27/12 

Once the t

OFF

 is determined at operating point B, the 

MOSFET conduction time is obtained as: 

@

@

min

@

@

1/

(1

)

S

OFF

B

ON

B

DL

B

S

P

O

B

F

f

t

t

V

N

N

V

V

=

+

+

 

(24)

 

Then, the transformer primary-side inductance can be 
calculated as: 

min

2

@

@

. @

(

)

2

DL

B

ON

B

m

S

IN T

B

V

t

L

f

P

=

 

 

(25) 

Once the transformer primary-side inductance is 
determined, DCM operation at operating point C should 
be checked. To prevent CCM operation, FAN302 
decreases the switching frequency as the output voltage 
drops, as illustrated in Figure 13. The switching frequency 
at the minimum output voltage is obtained as: 

@

.

@

@

.

(2.15

)

O

C

F SH

S

S

C

S

SH

A

N

SH

O

F SH

V

V

f

f

f

V

V

V

V

+

Δ

=

Δ

+

 

(26) 

where 

Δ

f

S

 / 

Δ

V

SH

  is  64 kHz / V  for  UL  version  and 

38 kHz / V for HL version, and V

F.SH

 is the rectifier 

diode forward voltage drop at the V

S

 sampling instant 

(85% of diode conduction time). 

Then, the MOSFET conduction time at operating point C 
is given as: 

. @

@

min

@

@

2

1

IN T

C

m

ON

C

DL

C

S

C

P

L

t

V

f

=

 

 

(27)

 

The non-conduction time at operating point C is given as: 

min

@

@

@

@

@

1

(1

)

DL

C

S

OFF

C

ON

C

S

C

P

O

C

F

V

N

t

t

f

N

V

V

=

+

+

 

 

(28) 

The non-conduction time should be larger than 15% of 
switching period, considering the transformer variation 
and frequency hopping. 

 

Figure 12. Variation of t

ON

, t

D

, and t

OFF

 

 

Figure 13. Frequency Reduction in CC Mode 

Once the transformer primary-side inductance is obtained, 
the maximum peak drain current can be calculated at the 
nominal output condition (operating point A) as: 

. @

2

IN T

A

PK

DS

m

S

P

I

L

f

=

(29)

The minimum number of turns for the transformer 
primary side to avoid the core saturation is given by: 

min

PK

m

DS

P

sat

e

L I

N

B

A

=

(30)

 

where AE is the cross-sectional area of the core in m

2

 

and B

sat

 is the saturation flux density in Tesla. Figure 14 

shows the typical characteristics of a ferrite core from 
TDK (PC40). Since the saturation flux density (B

sat

decreases as the temperature rises, the high temperature 
characteristics should be considered, especially for 
charger application in an enclosed case. If there is no 
reference data, use B

sat

=0.25~0.3T. With the turns ratio 

obtained in STEP-3, determine the proper integer for 

N

such that the resulting 

N

P

 

is larger than 

N

P

min

 

obtained 

from Equation (30). 

 

Figure 14. Typical B-H Curves of Ferrite Core 

(TDK/PC40) 

Summary of Contents for Fairchild FAN302HL

Page 1: ...y ON Semiconductor Typical parameters which may be provided in ON Semiconductor data sheets and or specifications can and do vary in different applications and actual performance may vary over time Al...

Page 2: ...nsformer and controlled with an internal compensation circuit This removes the output current sensing loss and eliminates all external current control circuitry facilitating a higher efficiency power...

Page 3: ...ycle As seen in Figure 2 the outputs of two comparators PWM I and PWM V are combined with the OR gate and used as a reset signal of flip flop to determine the MOSFET turn off instant The lower signal...

Page 4: ...on range since the output current can be properly estimated only in DCM as described in Section 2 As seen in Figure 5 the MOSFET conduction time tON decreases as output voltage decreases in CC Mode wh...

Page 5: ...FF C The overall power conversion efficiency should be estimated to calculate the input power and maximum DC link voltage ripple If no reference data is available use the typical efficiencies in Table...

Page 6: ...nt B are given as N O B O IN B FF B V I P E 9 N O B O IN T B FF S B V I P E 10 The overall efficiency at operating point C can be approximated as N O C O F FF C FF N O C F O V V V E E V V V 11 where V...

Page 7: ...he MOSFET drain to source voltage waveforms When the MOSFET is turned off the sum of the input DC link voltage VDL and the output voltage reflected to the primary side is imposed across the MOSFET cal...

Page 8: ...the power consumption of the IC by minimizing VDD at no load condition NA NS is determined as 1 6 STEP 4 Design the Transformer Figure 12 shows the MOSFET conduction time tON diode current discharge...

Page 9: ...point C is given as min 1 1 DL C S OFF C ON C S C P O C F V N t t f N V V 28 The non conduction time should be larger than 15 of switching period considering the transformer variation and frequency ho...

Page 10: ...as 2 P CCR CS N S O N V R N I K 31 where VCCR is 2 43 V and K 12 and 10 5 V for UL and HL respectively The voltage divider RVS1 and RVS2 should be determined so that VS is about 2 5 V at 85 of diode c...

Page 11: ...s related to the power dissipation in the clamping circuit Setting the voltage overshoot too low can lead to severe power dissipation in the clamping circuit For reasonable clamping circuit design vol...

Page 12: ...network is less than the designed value due to this effect 2 m OSS L C 2 LK OSS L C Figure 18 Drain Voltage Waveform Design Example Assuming that 700 V MOSFET is used the voltage overshoot to limit th...

Page 13: ...g frequency Design Example Assuming a 330 F tantalum capacitor with 100 m ESR for the output capacitor the voltage ripple on the output is 5 59 PK P C DS S N I I A N 2 0 592 2 N DIS A C O O C C O C t...

Page 14: ...L 51 Note that the effect of slope compensation is weaker at high line which increases the gain of control to output transfer function Thus the high line is the worst case for feedback loop design Si...

Page 15: ...or is used STEP 11 Choose Startup Resistor for HV Pin Figure 22 shows the high voltage HV startup circuit for FAN302 applications Internally the JFET is used to implement the high voltage current sour...

Page 16: ...ror amplifier output in normal operation During the load transient or abnormal condition such as output short the error amplifier can be saturated HIGH and the drain current is regulated by the pulse...

Page 17: ...ge traces related to the drain of the MOSFET and the RCD snubber should be away from control circuits to prevent unnecessary interference If a heat sink is used for the MOSFET connect this heat sink t...

Page 18: ...elds 18 H of effective leakage inductance Clamping circuit resistor R10 is adjusted to 390 k based on test results from the actual power supply Note that the sensing resistor is fine tuned to 1 2 base...

Page 19: ...Start Pin End Pin Turns W1 1 2 2UEW 0 15 2 8 2 W2 4 5 2UEW 0 12 1 22 0 22 1 22 3 W3 Fly Fly TEX E 0 4 1 5 3 Pin Specifications Remark Primary Side Inductance 4 5 530 H 7 100 kHz 1 V Primary Side Effec...

Page 20: ...2 shows the loss breakdown for the standby power consumption for 90 VAC and 264 VAC Figure 31 shows the measured output voltage and output current curve The output current is regulated between 1 A and...

Page 21: ...R USE OF ANY PRODUCT OR CIRCUIT DESCRIBED HEREIN NEITHER DOES IT CONVEY ANY LICENSE UNDER ITS PATENT RIGHTS NOR THE RIGHTS OF OTHERS LIFE SUPPORT POLICY FAIRCHILD S PRODUCTS ARE NOT AUTHORIZED FOR USE...

Page 22: ...the rights of others ON Semiconductor products are not designed intended or authorized for use as a critical component in life support systems or any FDA Class 3 medical devices or medical devices wit...

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