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AN-6094 
 

© 2012 Fairchild Semiconductor Corporation 

 

www.fairchildsemi.com 

Rev. 1.0.0  •  9/27/12 

13 

(Design Example)

 The original resonance period is 

measured as t

R

=25 ns. 

Using a 1 nF test capacitor, the resonance period is 
measure as t

RT

=25 ns. 

Then, the resonant parameters are obtained as: 

2

/[(

)

1] 395

RT

D

TST

R

t

C

C

pF

t

=

− =

 

2

1

(

)

40

2

R

LKS

D

t

L

nH

C

π

=

=

 

The snubber circuit parameters are calculated as: 

10

,

2.5

1

LKS

SNB

SNB

D

D

L

R

C

C

nF

C

=

= Ω

=

=

 

 

 

[STEP-10] Design the Feedback Loop  

Since the FAN302 operates a flyback converter in DCM 
with a peak-current mode control, the control to output 
transfer function of the power stage is given as: 

ˆ

1

ˆ

1

o

Z

V

FB

P

v

s

G

v

s

ω
ω

+

=

+

 

(49) 

where

2

p

L

OUT

R C

ω

=

1

Z

ES

OUT

R C

ω

=

; C

OUT

 is 

effective output capacitance; and R

ES

 is the effective 

series resistance of the output capacitor. 

The gain G

V

 of Equation (49) is defined as: 

1
3

N

O

V

a

CS DS

V

m

G

m

m

R

I

= ⋅

+

 

(50) 

where 1/3 is the attenuation factor of feedback voltage; 
I

DS

 is the peak drain current at given operating 

condition; m

a

 is the slope of slope compensation signal; 

and m is the slope of current sensing signal, given as: 

DL

CS

m

V

R

m

L

=

 

(51) 

Note that the effect of slope compensation is weaker at 
high line, which increases the gain of control-to-output 
transfer function. Thus, the high line is the worst case for 
feedback loop design.  

Since the control to output transfer function is first order, 
the feedback control loop can be implemented with a one-
pole and one-zero compensation circuit, as shown in 
Figure 20. The transfer function of the compensation 
network is given as: 

1

1

ˆ

(

1)

ˆ

(

1)

CZ

EA

I

o

CP

s

v

v

s

s

ω

ω

ω

+

=

+

 

(52) 

where 

1

FB

I

F

bias

FR

R

R R

C

ω

=

1

1

1

(

)

CZ

FR

F

FR

R

R

C

ω

=

+

and 

1

1

CP

FB

FB

R C

ω

=

Note that the opto-coupler introduces a mid-frequency 
pole due to the collector-emitter junction capacitance. 
Since the collector-base junction in a photo-transistor is 
used as a light detector; its area is relatively large, which 
introduces a large effective collector-emitter junction 
capacitance. The typical collector-emitter junction 
capacitance is about 3-10 

nF for the opto-coupler 

FOD817A, which brings a pole at around 1 kHz with a 
bias resistor of 42 k

Ω

, as shown in Figure 20. This pole 

can occur around the desired crossover frequency, making 
the system unstable. Therefore, this additional pole should 
be considered when designing the compensation network. 

 

Figure 20. Feedback Loop Circuit 

 

Figure 21. Frequency Response of Opto-Coupler 

 

Summary of Contents for Fairchild FAN302HL

Page 1: ...y ON Semiconductor Typical parameters which may be provided in ON Semiconductor data sheets and or specifications can and do vary in different applications and actual performance may vary over time Al...

Page 2: ...nsformer and controlled with an internal compensation circuit This removes the output current sensing loss and eliminates all external current control circuitry facilitating a higher efficiency power...

Page 3: ...ycle As seen in Figure 2 the outputs of two comparators PWM I and PWM V are combined with the OR gate and used as a reset signal of flip flop to determine the MOSFET turn off instant The lower signal...

Page 4: ...on range since the output current can be properly estimated only in DCM as described in Section 2 As seen in Figure 5 the MOSFET conduction time tON decreases as output voltage decreases in CC Mode wh...

Page 5: ...FF C The overall power conversion efficiency should be estimated to calculate the input power and maximum DC link voltage ripple If no reference data is available use the typical efficiencies in Table...

Page 6: ...nt B are given as N O B O IN B FF B V I P E 9 N O B O IN T B FF S B V I P E 10 The overall efficiency at operating point C can be approximated as N O C O F FF C FF N O C F O V V V E E V V V 11 where V...

Page 7: ...he MOSFET drain to source voltage waveforms When the MOSFET is turned off the sum of the input DC link voltage VDL and the output voltage reflected to the primary side is imposed across the MOSFET cal...

Page 8: ...the power consumption of the IC by minimizing VDD at no load condition NA NS is determined as 1 6 STEP 4 Design the Transformer Figure 12 shows the MOSFET conduction time tON diode current discharge...

Page 9: ...point C is given as min 1 1 DL C S OFF C ON C S C P O C F V N t t f N V V 28 The non conduction time should be larger than 15 of switching period considering the transformer variation and frequency ho...

Page 10: ...as 2 P CCR CS N S O N V R N I K 31 where VCCR is 2 43 V and K 12 and 10 5 V for UL and HL respectively The voltage divider RVS1 and RVS2 should be determined so that VS is about 2 5 V at 85 of diode c...

Page 11: ...s related to the power dissipation in the clamping circuit Setting the voltage overshoot too low can lead to severe power dissipation in the clamping circuit For reasonable clamping circuit design vol...

Page 12: ...network is less than the designed value due to this effect 2 m OSS L C 2 LK OSS L C Figure 18 Drain Voltage Waveform Design Example Assuming that 700 V MOSFET is used the voltage overshoot to limit th...

Page 13: ...g frequency Design Example Assuming a 330 F tantalum capacitor with 100 m ESR for the output capacitor the voltage ripple on the output is 5 59 PK P C DS S N I I A N 2 0 592 2 N DIS A C O O C C O C t...

Page 14: ...L 51 Note that the effect of slope compensation is weaker at high line which increases the gain of control to output transfer function Thus the high line is the worst case for feedback loop design Si...

Page 15: ...or is used STEP 11 Choose Startup Resistor for HV Pin Figure 22 shows the high voltage HV startup circuit for FAN302 applications Internally the JFET is used to implement the high voltage current sour...

Page 16: ...ror amplifier output in normal operation During the load transient or abnormal condition such as output short the error amplifier can be saturated HIGH and the drain current is regulated by the pulse...

Page 17: ...ge traces related to the drain of the MOSFET and the RCD snubber should be away from control circuits to prevent unnecessary interference If a heat sink is used for the MOSFET connect this heat sink t...

Page 18: ...elds 18 H of effective leakage inductance Clamping circuit resistor R10 is adjusted to 390 k based on test results from the actual power supply Note that the sensing resistor is fine tuned to 1 2 base...

Page 19: ...Start Pin End Pin Turns W1 1 2 2UEW 0 15 2 8 2 W2 4 5 2UEW 0 12 1 22 0 22 1 22 3 W3 Fly Fly TEX E 0 4 1 5 3 Pin Specifications Remark Primary Side Inductance 4 5 530 H 7 100 kHz 1 V Primary Side Effec...

Page 20: ...2 shows the loss breakdown for the standby power consumption for 90 VAC and 264 VAC Figure 31 shows the measured output voltage and output current curve The output current is regulated between 1 A and...

Page 21: ...R USE OF ANY PRODUCT OR CIRCUIT DESCRIBED HEREIN NEITHER DOES IT CONVEY ANY LICENSE UNDER ITS PATENT RIGHTS NOR THE RIGHTS OF OTHERS LIFE SUPPORT POLICY FAIRCHILD S PRODUCTS ARE NOT AUTHORIZED FOR USE...

Page 22: ...the rights of others ON Semiconductor products are not designed intended or authorized for use as a critical component in life support systems or any FDA Class 3 medical devices or medical devices wit...

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