Omega ISA- BUS MULTI-FUNCTIONAL BOARD OME-A822PG Hardware Manual Download Page 47 | Manualshive

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Although you can continue by pressing any key, it is recommended that the jumper

situation be corrected since many operations in the

A82XDIA

utility check the I/O

base address and report an error if the configuration file and the actual jumper settings do
not match.

OME-A-822PGL/PGH Hardware Manual ----

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Summary of Contents for ISA- BUS MULTI-FUNCTIONAL BOARD OME-A822PG

Page 1: ...www omega com e mail info omega com User sGuide OME A822PG ISA Bus Multi Functional Board Hardware Manual Shop online at...

Page 2: ...court France TEL 33 0 1 61 37 29 00 FAX 33 0 1 30 57 54 27 Toll Free in France 0800 466 342 e mail sales omega fr Germany Austria Daimlerstrasse 26 D 75392 Deckenpfronn Germany TEL 49 0 7056 9398 0 FA...

Page 3: ...OME A 822PGH PGL Enhanced Multi Function Card Hardware Manual OME A 822PGL PGH Hardware Manual 1...

Page 4: ...___________________________________________ 10 2 3 Jumper Settings______________________________________________________ 11 2 3 1 JP1 D A Internal Reference Voltage Selection__________________________...

Page 5: ...______________________________________________ 40 3 2 1 OME DB 8225 ____________________________________________________________ 40 3 2 2 OME DB 37 ____________________________________________________...

Page 6: ...performance bench marks were achieved on a 33MHz 486 computer z Polling mode about 100Ksample sec with single task OS z Interrupt mode about 60Ksample sec with single task OS z DMA mode about 100Ksamp...

Page 7: ...to 1 25 V OME A 822PGH bipolar 10 5V 1V 0 5V 0 1V 0 05V 0 01V 0 005V unipolar 0 to 10V 0 to 1V 0 to 0 1V 0 to 0 01V z Input current 250 nA max 125 nA typical at 25 deg C z On chip sample and hold z Ov...

Page 8: ...ive 5mA z settling time 0 6 microseconds to 0 01 for full scale step 1 3 5 Digital I O z Output port 16 bits TTL compatible Output Low VOL 05 Vmax IOL 8 mA max Output High VOH 2 7Vmin IOH 400 A max z...

Page 9: ...also uses counter0 to implement a machine independent timer z Clock input frequency DC to 10 MHz z Pacer output 0 00047Hz to 0 5MHz z Input gate TTL compatible z Internal Clock 2 MHz 1 3 8 Direct Mem...

Page 10: ...urement and control 1 5 Product Check List The OME A 8322PGL PGH includes the following items z OME A 822PGL PGH multifunction card z OME A 822PGL PGH CD ROM Attention If any of these items are missin...

Page 11: ...2 Hardware Configuration 2 1 Board Layout OME A 822PGL PGH VR1 2 3 4 5 6 7 ISA BUS ISA BUS CN2 CN1 JP5 SW1 CN3 JP3 JP6 JP8 JP7 JP4 JP1 JP2 OME A 822PGL PGH Hardware Manual 9...

Page 12: ...W1 The default address is 0x220 A9 A8 A7 A6 A5 A4 6 5 4 3 2 1 ON SW1 BASE ADDRESS BASE ADDR A9 A8 A7 A6 A5 A4 200 20F OFF ON ON ON ON ON 210 21F OFF ON ON ON ON OFF 220 22F OFF ON ON ON OFF ON 230 23F...

Page 13: ...F EGA 2E0 2E7 AT GPIB 3D0 3DF CGA 2E8 2EF Serial Port 3E8 3EF Serial Port 2F8 2FF Serial Port 3F0 3F7 Floppy Disk 300 31F Prototype Card 3F8 3FF Serial Port 2 3 Jumper Settings 2 3 1 JP1 D A Internal...

Page 14: ...2 2 3 3 JP3 Single ended Differential Selection Ch 1 INT Ch 2 INT default JP2 vref Ch 1 EXT ExtRef1 Ch 2 EXT ExtRef2 JP2 vref Ch 1 INT Ch 2 EXT ExtRef2 JP2 vref Ch 1 EXT ExtRef1 Ch 2 INT JP2 vref DIFF...

Page 15: ...s of internal triggers software trigger and pacer trigger More detailed information is given in section 2 4 8 2 3 5 JP5 Interrupt Level Selection NO Interrupt IRQ 3 4 5 6 7 9 10 11 12 14 15 NC Interru...

Page 16: ...et to 2M internal clock or external clock ExtCLK CN3 pin 37 The block diagram is given in section 2 6 The clock source must be very stable Using the 2M internal clock is strongly suggested The OME A 8...

Page 17: ...JP7 1 5 2 6 DRQ 1 5 2 6 DACK DMA 1 default JP8 JP7 1 5 2 6 DRQ DACK 1 5 2 6 DMA 3 The DMA channel can not shared The OME A 822 software driver can support 8 different boards in one PC based system but...

Page 18: ...unter Control Base 4 A D Low Byte D A Channel 0 Low Byte Base 5 A D High Byte D A Channel 0 High Byte Base 6 DI Low Byte D A Channel 1 Low Byte Base 7 DI High Byte D A Channel 1 High Byte Base 8 Reser...

Page 19: ...gister READ Base 4 A D Low Byte Data Format Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 D7 D6 D5 D4 D3 D2 D1 D0 READ Base 5 A D High Byte Data Format Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit...

Page 20: ...o an analog output The lower 8 bits of D A channel 1 are stored in the address BASE 4 and the high 4 bits are stored in the address BASE 5 The address BASE 6 and BASE 7 store the 12 bit data for D A c...

Page 21: ...BASE 6 The high 8 bits are stored in address BASE 7 2 4 5 Clear Interrupt Request WRITE Base 8 Clear Interrupt Request Format Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 X X X X X X X X X don t ca...

Page 22: ...for the different gain control codes The software driver does not take care the gain settling time so the user needs to add the delay If the application program will run on different machines the user...

Page 23: ...t Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 X X X X D3 D2 D1 D0 A D input channel selection data 4 bits D3 D0 D3 MSB D0 LSB X don t care Single ended mode D3 D0 Differential mode D2 D0 D3 don t...

Page 24: ...ransfer stage The trigger stage will generate a trigger signal to the A D converter and the transfer stage will transfer the result to the CPU The trigger method may be internal trigger or external tr...

Page 25: ...Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 X X X X X X X X X don t care XXXXXXXX any 8 bits data is validate The A D converter can be triggered by software trigger or pacer trigger The details are give...

Page 26: ...Base E D O Output Latch High Byte Data Format Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 D15 D14 D13 D12 D11 D10 D9 D8 D O 16 bits output data D15 D0 D15 MSB D0 LSB The OME A 822PGL PGH provides...

Page 27: ...below Latch Reset Power on reset Reset Latch D0 D7 Base D Base E D0 D7 D8 D15 1 8 9 16 Output Latch Register Output Latch Register CN2 17 18 DGND DGND DI TTL External Device OME A 822PGL PGH Read Rea...

Page 28: ...LK VCC 10K CN3 37 PACER CLK JP6 2M CN3 35 CN3 16 CN3 33 VCC 10K CN3 34 The counter0 counter1 and counter2 are all 16 bit counters Counter 1 and counter 2 are cascaded as a 32 bit timer This 32 bit tim...

Page 29: ...put channel sec 2 4 7 z A D mode control register BASE B selects the trigger type and transfer type sec 2 4 8 z A D software trigger control register is BASE C sec 2 4 9 z JP3 selects single ended or...

Page 30: ...tling time of multiplexer depends on the source resistance Because the software doesn t account for the settling time the user should provide sufficient delay when switching channels sec 2 4 7 The gai...

Page 31: ...nsfer This mode can be used with all trigger modes More detailed information is given in section 2 4 8 The software scans the A D high byte data register BASE 5 until READY_BIT 0 The low byte data is...

Page 32: ...r to the multiplexer control register refer to Sec 2 4 7 3 send the gain control code value to the gain control register refer to Sec 2 4 6 4 delay the settling time refer to Sec 2 4 6 and Sec 2 4 7 5...

Page 33: ...If JP2 is set to internal and JP1 is set to 10V the D A output range is 0 to 10V z If JP2 is set to external the external reference voltage can be AC DC 10V The block diagram is given below OME A 822P...

Page 34: ...s connected to a source with a common mode voltage greater than 70Vp p the input multiplexer will be permanently damaged When measuring common mode voltage it is best to use an oscilloscope rather tha...

Page 35: ...Figure 1 A Figure 1 B If the source is grounded a second ground connection on the card could result in a ground loop OME A 822PGL PGH Hardware Manual 33...

Page 36: ...Figure 2 Figure 3 OME A 822PGL PGH Hardware Manual 34...

Page 37: ...4 20mA to 1 5Vdc Signal Shielding z The signal shielding is the same for the connections shown in Figure 1 to Figure 4 z Use a single connection to frame ground not A GND or D GND Vin Frame Ground OME...

Page 38: ...to 2 3 single ended mode 4 Read the temperature from a digital thermometer placed near D1 D2 See the OME DB 8225 Layout 5 Read OME A 822PGL PGH analog input channel 0 single ended Channel 0 6 Adjust...

Page 39: ...0 Digital Input 9 TTL 11 Digital Input 10 TTL 12 Digital Input 11 TTL 13 Digital Input 12 TTL 14 Digital Input 13 TTL 15 Digital Input 14 TTL 16 Digital Input 15 TTL 17 GND 18 GND 19 5V Output 20 12V...

Page 40: ...log GND 10 Analog GND 29 Analog GND 11 D A internal 5V 10V voltage reference 30 D A channel 0 analog voltage output 12 D A channel 1 external voltage reference input 31 D A channel 0 external voltage...

Page 41: ...10 Analog GND 29 Analog GND 11 D A internal 5V 10V voltage reference output 30 D A channel 0 analog voltage output 12 D A channel 1 external voltage reference input 31 D A channel 0 external voltage...

Page 42: ...al board It connects to a 37 pin D sub connector 3 2 3 OME DB 16P The OME DB 16P is a 16 channel isolated digital input board The OME A 822PGL PGH provides 16 channels of non isolated TTL compatible d...

Page 43: ...m this program included with the OME A822PGL PGH 4 1 Description of Variable Resistors There are seven variable resistors VRs on the OME A 822PGL PGH used for calibration they are described below VR N...

Page 44: ...N3 to a DVM Digital Volt Meter 6 Adjust VR5 until the DVM 4 9988V 7 Press the ESC Key 8 Select and Execute A D A REFERENCE 1 item 9 Connect D A channel 0 pin 30 of CN3 to the DVM 10 Adjust VR3 until t...

Page 45: ...le 0V to A D channel 0 pin1 of CN3 10 Adjust VR1 until the A D data shown on the screen is between 2048 to 2049 11 Press the ESC Key 12 Repeat step_3 to step_11 until there is no need to adjust VR2 VR...

Page 46: ...n file named OME A 82X CFG is associated with the A82XDIAG EXE program The configu ration of the OME A 822PGL PGH board is stored in this file The stored information includes the board s I O base addr...

Page 47: ...s recommended that the jumper situation be corrected since many operations in the A82XDIA utility check the I O base address and report an error if the configuration file and the actual jumper setting...

Page 48: ...he Left or Right key to select the main menu Then use the Up or Down key to select the menu item Alternately the user can press the command key to highlight the menu item A command key in a menu item...

Page 49: ...822PGL PGH Enter key to select Base Address Up Down key to select base address Enter key to select DMA no Up Down key to select DMA no Enter key to select IRQ no Left Right key to select IRQ no Enter...

Page 50: ...DMA no and IRQ no selection screen OME A 822PGL PGH Hardware Manual 48...

Page 51: ...the OME A 822PGL PGH board layout In order to maintain the specified performance it may be required to calibrate the board after working with it for an extended period of time There are seven variabl...

Page 52: ...CTION TEST main menu contains seven submenus they are D A TEST Digital I O A D MULTIPLEX A D use IRQ A D use DMA A D GAIN Timer 0 The main menu is shown below The D A TEST menu is shown below OME A 82...

Page 53: ...to 5V z Send D A output to both channels simultaneously z Press p pause screen press p again release screen z Press Up key to increase screen delay z Press Down key to decrease screen delay z Press ES...

Page 54: ...hannel DI are readback and show on the screen z If DO equals DI then OK shown on screen z If DO does not equal DI then Error shown on screen z Press p pause screen press p again release screen z Press...

Page 55: ...tiplexer Test Screen z Assume 16 channel single ended bipolar gain 1 analog input signals z Input range from 5V to 5V z Continue to scan 16 channels z Press ESC key to quit OME A 822PGL PGH Hardware M...

Page 56: ...se Left Right key to adjust C2 z The sample rate The pacer timer rate 2000 C1 C2 K z Use p key to pause screen use next p key to release screen z Use ESC to quit z The A D mode control register 0x06 s...

Page 57: ...st C1 z Use Left Right key to adjust C2 z Sample rate pacer timer rate 2000 C1 C2 K z Use p key to pause screen use next p key to release screen z Use ESC to quit z A D mode control register 0x02 sele...

Page 58: ...gain 1 A D channel 0 connected to D A channel 0 z Use Up Down key to adjust gain control code z Use Left Right key to adjust D A output value z Use software trigger and polling transfer mode z Press E...

Page 59: ...Timer 0 Test Screen z Assume JP6 set to internal 2M clock z If the counter0 is functioning normally the value will increment automatically OME A 822PGL PGH Hardware Manual 57...

Page 60: ...TEST The SPECIAL TEST menu contains four submenu items they are D A Volt Set DIO Bit Pattern IRQ Clock Test and DMA Clock Test These functions are reserved for factory testing OME A 822PGL PGH Hardwa...

Page 61: ...5 2 5 Help The Help menu will display the software version as shown below OME A 822PGL PGH Hardware Manual 59...

Page 62: ...shall not exceed the purchase price of the component upon which liability is based In no event shall OMEGA be liable for consequential incidental or special damages CONDITIONS Equipment sold by OMEGA...

Page 63: ...city Indicators Turbine Paddlewheel Systems Totalizers Batch Controllers pH CONDUCTIVITY pH Electrodes Testers Accessories Benchtop Laboratory Meters Controllers Calibrators Simulators Pumps Industria...

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