2.4.8 A/D Mode Control Register
(WRITE) Base+B : A/D Mode Control Register Format
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
X X X X X D2 D1 D0
X=don‘t care
JP4 Select Internal Trigger
Mode Select Trigger Type
Transfer Type
D2 D1 D0 Software Trig
Pacer Trig
Software Interrupt DMA
0 0 0 X
X
X
X
X
0 0 1 Select
X
Select X
X
0 1 0 X
Select
X
X
Select
1 1 0 X
Select
Select Select X
X=disable
JP4 Select External Trigger
Mode Select Trigger Type
Transfer Type
D2 D1 D0 External Trigger
Software Interrupt DMA
0 0 0 X
X
X
X
0 0 1 X
X
X
X
0 1 0 Select
X
X
Select
1 1 0 Select
Select Select X
The A/D conversion can be divided into 2 stages,
trigger stage and transfer stage
. The
trigger stage will generate a trigger signal to the A/D converter and the transfer stage will
transfer the result to the CPU.
The trigger method may be
internal trigger
or
external trigger.
The internal trigger can
be
software trigger
or
pacer trigger.
The software trigger is simple to use but does not
control the sampling rate very precisely.
In the software trigger mode, the program issues
a software trigger command (sec 2.4.9) to initiate the A/D conversion. The program then
must poll the A/D status bit until the ready bit is 0(sec 2.4.2).
The pacer trigger can control the sample rate very precisely.
In the pacer trigger
mode, the pacer timer (sec 2.6) will generate periodic trigger signals to the A/D converter.
The converted data can be transferred to the CPU by polling or interrupt or by DMA transfer.
OME-A-822PGL/PGH Hardware Manual ----
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