FM TRANSMITTER
TR
EM
1000
HE
DIG
PLUS
COMPACT
Technical Manual 1v2 November 2019
64
3.2 FM SYNTHESIZER
This unit includes a classical phase-locked-loop circuit with 10 kHz-step synthesis across the
entire FM band. The very low-noise, fundamental-frequency VCO (Voltage-Controlled
Oscillator) consists of a FET oscillator transistor TR5, modulated by the varactor diode set
D4~D7, which also sets the operating frequency. The circuit is sensitivity compensated vs.
carrier frequency variation so that its modulation gain varies less then 0.5dB across the entire
operating range. Modulation distortion is typically lower than 0.03 % with over 90dB S/N ratio
in the mono mode in the 30 - 20,000Hz band.
The RF signal is buffered and amplified by three successive transistors TR6 ~ TR8, from which
is derived the feedback signal to the PLL and the drive signal for the output RF stage. This
latter is composed by two small MOSFET transistors TR9 and TR10 and attains some 900mW
output level (+29dBm) over the full FM range. To correctly operate TR9 and TR10 require a
gate bias voltage, which is factory pre-set by RT1.
Figure: FM synthesizer
The digital PLL circuit is entirely contained in IC2, whose frequency reference is derived by a
highly precise temperature compensated oscillator (TCXO1) running at 12.8MHz. To correctly
operate on the chosen frequency, IC2 must be serially programmed with complex data. This
task is done by the Exciter's Microcontroller through 3 control lines.
IC1 either performs loop filtering from IC2 frequency comparator output to the varactor
diodes and lock detection. Note that bias voltage is removed from output transistors through
TR4 and TR3 to turn off RF when the PLL is not locked on the right frequency. The control loop
was designed to ensure that crosstalk added to stereo-composite signal is below -55dB at
30Hz, and is virtually not influent at just slightly higher frequencies.