H-3
Ver. 1
H. DESCRIPTION OF MECHANISM
C-7070 Wide Zoom
Fig. 1-3. IC991 and IC992 Block Diagram
3. IC906 (H Driver) and IC991, IC992 (V Driver)
An H driver (a part of IC906) and V driver (IC991 and IC992)
are necessary in order to generate the clocks (vertical
transfer clock, horizontal transfer clock and electronic shut-
ter clock) which driver the CCD.
IC906 has clock generating which drives horizontal CCD
and its drives function. These clocks are output from pin
(14), (15), (18) and (19) of IC906. In addition the XV1-XV8
signals which are output from IC101 are the vertical trans-
fer clocks, and the XSG1A, XSG1B, XSG3A, XSG3B, XSG5A,
XSG5B, XSG7A and XSG7B signals which are output from
IC102 is superimposed onto XV1, XV3, XV5 and XV7 at
IC991 in order to generate a ternary pulse. In addition, the
XSUB signal which is output from IC101 is used as the
sweep pulse for the electronic shutter, and the RG signal
which is output from pin (21) of IC906 is the reset gate
clock.
4. IC906 (CDS, AGC Circuit and A/D Converter)
The video signal which is output from the CCD is input to
pins (27) of IC906. There are S/H blocks inside IC905
generated from the XSHP and XSHD pulses, and it is here
that CDS (correlated double sampling) is carried out.
After passing through the CDS circuit, the signal passes
through the AGC amplifier. It is A/C converted internally
into a 12-bit signal, and is then input to IC102 of the CP1
circuit board. The gain of the AGC amplifier is controlled
by pin (31)-(33) serial signal which is output from IC101 of
the CP1 board.
Fig. 1-4. IC906 Block Diagram
1
21
10
9
8
7
6
5
4
3
2
17
18
19
20
23
22
14
15
16
V2
VL
V3A
V3B
VH
V5A
V5B
VM
V4
V6
XV5
V
DD
XSUB
XV1
XV2
XSG3A
XSG3B
XV3
XSG5A
Input Buffer
XSG1
11
XSG5B
12
XV4
13
XV6
24
V1
25
SUB
26
MODE
(High)
CCDIN
RG
H1-H4
VD
HD
SDATA
SCK
SL
CLI
HBLK
CLP/PBLK
DOUT
VRB
VRT
PRECISION
TIMING
CORE
SYNC
GENERATOR
PxGA
VGA
12-BIT
ADC
12
6~42 dB
VREF
CLAMP
INTERNAL
REGISTERS
INTERNAL
CLOCKS
CDS
HORIZONTAL
DRIVERS
4
0~18 dB
AD9949
