OKIDATA Pacemark 3410, Service Handbook

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2.1.05 Printhead Drive Circuit
This circuit is used to drive the 9 print wires. The signals HD01 through HD09 from Q2 are
used to enable the individual wire drivers (TRA1 and TRA2). TRA1 drives Pins 1, 2, 6 and 7.
TRA2 drives Pins 3, 4, 8 and 9. TR7 drives Pin 5. The HD ON signal enables the drive circuit
when printing is desired. The head drive duration is determined by an RC integrating circuit
which modifies the HD ON pulsewidth. The pulsewidth of the HD ON signal varies with the
number of pins being driven. The drive time is increased as a greater number of pins are driven,
but decreased as less pins are to be driven. The drive time is also increased if the head gap lever
in placed in positions 3 through 9. The RC circuit is also used to compensate for the fluctuation
of drive voltage (+38vdc).
2.1.06 Spacing Drive Circuit
After receiving a spacing command from the MPU (Q3), the Interface/Motor Control LSI (Q5)
outputs the SPFWD signal to run the DC motor in the forward direction, or the SPRVS signal to
run the DC motor in the reverse direction. This is a fixed pulsewidth signal.
To control the motor speed, Q5 varies the pulse duty cycle according to feedback received from
the space motor. As the space motor rotates, the SPSP Board (inside the motor housing)
generates feedback pulse signals SP
φ
A and SP
φ
B. Q5 detects the edge pulses from these signals
and divides the frequency to output the IPT signal for use in printhead dot timing.
The space motor interlock switch (located at the left side of the shield plate) disables the space
motor drive signals whenever the printer cover is open.
Fuse F1 (3.5 amperes) protects the +38vdc space motor power circuit, should an overdrive
condition exist.
2-E.pcx
2-D.pcx
Principles of Operation 2 - 8 Pacemark 3410