Oki TF-300P, Field Service Manual

Page: 48 / 137

6-9
TSTCLK
REGDMA
WAITn
WRn,RDn
A[19:0]
Ext. CS's
CS[4:3]n
D[7:0]
(Read)
D[7:0]
(Write)
D[7:0]
(Internal)
Access with 1 Wait State Access with 0 Wait States
t
RGD
t
DMD
t
WSD
t
SD
t
SDD
t
AD
t
SDE
t
CSD
t
CGD
t
CGD
t
WSD
t
SD
t
SD
t
SD
t
RGD
t
DMD
t
DDW
t
DH
t
DDW
t
DS
t
DHR
t
DDI
t
DH
t
DH
t
DS
t
DHR
O U T
O U T O U T
I N IN
DM A R E G SE L
A cc
D M A A cce ss R EG S E L
Figure 6-4 External bus data access timing
Table 6-4 External Bus Signal Timing Parameters
Parameter Symbol Min. Max. Units
SYSCLK cycle tSCY 50 - ns
SYSCLK pulse width high tSH 22 - ns
SYSCLK pulse width low tSL 22 - ns
TSTCLK delay tCD - 20 ns
SYNC delay tSYD - 30
tSL+10
ns
RDY access delay tRDY - 7 ns
/DEBUG setup tDBS 20 - ns
/DEBUG hold tDBH 0 - ns
Interrupts setup tIS 15 - ns
Interrupts hold tIH 0 - ns
BE setup tHS 15 - ns
BE hold tHH 0 - ns
REGDMA delay (CPU register
access) tRGD - 30
tSL+10
ns