Oki ML66592, User Manual

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15
MSM66591/ML66592 User's Manual
Chapter 15 Serial Port Functions
[2] 4-Stage Buffer Mode
The 4-stage buffer mode is entered by setting SRnEXP (bit 3) of SRnCON. During the
4-stage buffer mode, consecutive reception of up to a maximum of 4 bytes is possible.
After 4 bytes are received, they can be collectively processed by an interrupt.
<4-Stage Buffer Mode with UART Reception: SCI0 Example>
During the 4-stage buffer mode, the receive buffers form a ring buffer configuration. At
the completion of each 1-byte reception, the contents of the receive register (receive
data) are transferred to a receive buffer in the order of S0BUF0, S0BUF1, S0BUF2,
S0BUF3, S0BUF0, etc. Therefore, data is received up to the S0BUFn receive buffer
(where n = 0 to 3). After processing that data, if reception is continued, data is received
beginning from the S0BUF(n + 1) buffer.
For example, after receiving data up to S0BUF1 and processing that data, the next data
reception begins with S0BUF2. Or, after receivingdata up to S0BUF3 and processing
that data, the next data reception begins with S0BUF0.
After receiving data up to S0BUFn and processing that data, if it is desired to receive m
consecutive bytes (m
≤
4) of data and then process that data by an interrupt, since an
interrupt will be generated after data is received in the S0BUF(n + 1) through S0BUF(n
+ m) buffers, enable interrupt requests for S0BUF(n + m), the last buffer to receive data,
and then receive the data.
For example, after completing processing up to S0BUF2, if it is desired to receive 3
consecutive bytes of data and then process that data by an interrupt, since the 3 bytes
of data will be received in the order of S0BUF3, S0BUF0, and S0BUF1, enable interrupt
generation only for S0BUF1, the last buffer to receive data, and then begin the data
reception. To enable interrupt generation for S0BUF1, set RV0IE1 (SCI0 receive
interrupt enable flag) of SR0INT to "1". In this case, after reception is completed for
S0BUF3 through S0BUF1, an SCI0 receive complete interrupt request is generated,
and the SCI0 receive interrupt request flags (RV0IRQ1 of SR0INT and QSCI0 of
IRQ1L) are set.
Because a parity error flag, multiprocessor communication flag and overrun error flag
are provided for each receive buffer (4 bits in total), data reception errors can be
verified by reading the error flags that correspond to buffers. The framing error flag
consists of 1 bit. If a framing error occurs even in just 1 byte of the received data, the
framing error flag will be set to "1" at that time.
If 5 or more bytes of data are consecutively received, new data will overwrite the pre-
vious data, beginning with the receive buffer that received the first data. At that time, if
the data transferred to the receive buffer during the previous receive operation has not
been read by the CPU, the overrun error flag of each receive buffer will be set to "1".
After a framing or other error has occurred, read BFCU00 (bit 4) and BFCU01 (bit 5) of
S0STAT2 to verify which receive buffer will data be transferred to at the completion of
the next reception.
Receive timing in 1 frame of the 4-stage buffer mode is controlled in the same manner
as reception in the single buffer mode.
SCI2, SCI3 and SCI4 also operate in the same manner.
Figure 15-36 shows a timing example of the 4-stage buffer mode with UART reception.