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Oki ML66592, User Manual

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9-2

MSM66591/ML66592 User's Manual
Chapter 9   Time Base Counter (TBC)

9.1

1/n Counter

The MSM66591/ML66592 have a 4-bit auto-reload timer that uses a CLK as the input
clock, therefore the same clock pulse (TBCCLK) can be supplied to TBC, even if the
original oscillation frequency is changed.

The 1/n counter consists of a 4-bit counter (TBCKDVC) and a 4-bit register (TBCKDVR)
to store reload values.

TBCKDVC

TBCKDVC is a 4-bit counter that uses a CLK (clock generated by multiplying the
original oscillation clock by 2) as the input clock. Write is invalid. Read is valid, but the
high-order 4 bits will read "1" if read. At reset (when the 

RES

 signal is input, the BRK

instruction is executed, the watchdog timer is overflown, or an operation code trap is
generated), TBCKDVC becomes F0H.

TBCKDVR

TBCKDVR is a 4-bit register that stores reload values into TBCKDVC.

Write is valid, but write to high-order 4 bits is invalid. Read is valid, but the high order 4
bits will read "1" if read.

At reset (when the 

RES

 signal is input, the BRK instruction is executed, the watchdog

timer is overflown, or an operation code trap is generated), TBCKDVR becomes F0H.
At reset the 1/n counter divides the 1 CLK into 16, and supplies a 1/16 CLK to TBC as
TBCCLK.

After writing a reload value to TBCKDVR, the dividing operation may delay for a maxi-
mum of 16 clocks of CLK, depending on the dividing ratio written to TBCKDVR.

The following table shows 1/n counter correspondence between the dividing ratios and
the values to be set to TBCKDVR.

Dividing ratio

Value to TBCKDVR

Dividing ratio

Value to TBCKDVR

1/1

FFH

1/2

FEH

1/3

FDH

1/4

FCH

1/5

FBH

1/6

FAH

1/7

F9H

1/8

F8H

1/9

F7H

1/10

F6H

1/11

F5H

1/12

F4H

1/13

F3H

1/14

F2H

1/15

F1H

1/16

F0H

—

—

—

—

7

6

5

4

3

2

1

0

—

—

—

—

7

6

5

4

3

2

1

0

Summary of Contents for ML66592

Page 1: ...MSM66591 ML66592 User s Manual CMOS 16 bit microcontroller FEUL66591 66592 01 Issue Date Mar 4 2002 ...

Page 2: ...ction set Description of addressing modes MAC66K Assembler Package User s Manual Package overview Description of RAS66K relocatable assembler operation Description of RAS66K assembly language Description of RL66K linker operation Description of LIB66K librarian operation Description of OH66K object converter operation Macroprocessor MP User s Manual Description of MP operation Description of macro...

Page 3: ...vel of the low side of the voltage indicates voltage level of VIL and VOL described in the electrical characteristics Opcode trap Operation code trap Occurs when an empty area that has not been assigned an instruction is fetched or when an instruction code combination that does not contain an instruction is addressed n Register description 7 6 SCNC0 5 SNEX0 4 ADRUN0 3 0 2 1 ADSNM02 ADSNM01ADSNM00 ...

Page 4: ...put Pins 2 4 2 8 P7_0 P7_7 Input Output Pins 2 5 2 9 P8_0 P8_7 Input Output Pins 2 6 2 10 P9_0 P9_7 Input Output Pins 2 6 2 11 P10_0 P10_7 Input Output Pins 2 7 2 12 P11_0 P11_7 Input Output Pins 2 8 2 13 P12_0 P12_1 Input Output Pins 2 9 2 14 AI0 AI23 Input Pins 2 9 2 15 AVDD Input Pin 2 9 2 16 VREF Input Pin 2 9 2 17 AGND Input Pin 2 9 2 18 OSC0 OSC1 Input Pin Output Pin 2 9 2 19 OE Input Pin 2 ...

Page 5: ...a Memory Access 3 12 1 Byte Operation 3 12 2 Word Operation 3 12 3 2 Registers 3 13 3 2 1 Arithmetic Register ACC 3 13 3 2 2 Control Register 3 14 1 Program Status Word PSW 3 14 2 Program Counter PC 3 17 3 Local Register Base LRB 3 17 4 System Stack Pointer SSP 3 18 3 2 3 Pointing Register PR 3 19 3 2 4 Local Registers R ER 3 20 3 2 5 Segment Register 3 21 1 Code Segment Register CSR 3 21 2 Table ...

Page 6: ...ardware Configuration of Each Port 6 1 6 1 1 Configuration of Type A P0_0 P0_7 P1_0 P1_7 P12_0 6 4 6 1 2 Configuration of Type B P2_0 P2_7 P3_0 P3_3 P7_4 P7_7 P8_0 P8_7 P10_0 P10_4 6 5 6 1 3 Configuration of Type C P3_4 P3_7 P4_0 P4_7 P5_0 P5_7 P6_0 P6_7 P7_2 P7_3 P9_0 P9_7 P10_5 P10_7 P11_0 P11_3 6 6 6 1 4 Configuration of Type D P7_0 P7_1 P11_4 P11_7 6 7 6 1 5 Configuration of Type E P12_1 6 7 6...

Page 7: ... 2 Chapter 11 Flexible Timer FTM 11 1 Configuration of Counter Part 11 6 11 2 Counter Selection Part 11 8 11 3 Type A1 Register Modules TMR0 TMR3 11 10 11 3 1 Configuration of Type A1 Register Modules TMR0 TMR3 11 10 1 Timer Registers TMR0 TMR0L TMR3 TMR3L 11 10 2 Capture Control Register CAPCON 11 11 3 Event Control Registers EVNTCONL EVNTCONH 11 12 4 Event Dividing Counters 0 3 EVDV0 EVDV3 11 14...

Page 8: ...utput Control Registers RTOCON4 RTOCON13 11 24 11 5 2 Operation of Type B Register Modules TMR4 TMR13 11 26 11 6 Type D Register Module TMR17 11 27 11 6 1 Configuration of Type D Register Module TMR17 11 27 1 Timer Register TMR17 11 29 2 Real time Output Control Registers RTOCON17 RTO4CON 11 29 3 TMR Mode Register TMRMODE 11 31 4 Capture Control Register CAPCON 11 32 11 6 2 Operation of Type D Reg...

Page 9: ...on of PWM 13 4 1 PWM Counters PWC0 PWC11 13 4 2 PWM Counter Buffer Registers PWC0BF PWC11BF 13 4 3 PWM Registers PWR0 PWR11 13 5 4 PWM Buffer Registers PW0BF PW11BF 13 5 5 Comparison Circuit 13 5 6 Output F F 13 5 7 PWM Control Registers PWCON0 PWCON5 13 5 8 PWMRUN Register PWRUN 13 9 9 PWM Interrupt Registers PWINTQ0 PWINTQ1 13 10 10 PWM Interrupt Enable Registers PWINTE0 PWINTE1 13 13 13 2 Opera...

Page 10: ...figuration of Serial Ports 15 2 15 2 Serial Port Control Registers 15 5 15 2 1 Control Registers for SCI0 15 5 1 SCI0 Transmit Control Register ST0CON 15 5 2 SCI0 Receive Control Register SR0CON 15 7 3 SCI0 Transmit Receive Buffer Register S0BUF0 15 9 4 SCI0 Receive Buffer Registers S0BUF1 S0BUF2 S0BUF3 15 9 5 SCI0 Transmit and Receive Registers 15 9 6 SCI0 Status Register 0 S0STAT0 15 10 7 SCI0 S...

Page 11: ...ve Buffer Registers S3BUF1 S3BUF2 S3BUF3 15 44 5 SCI3 Transmit and Receive Registers 15 44 6 SCI3 Status Register 0 S3STAT0 15 45 7 SCI3 Status Register 1 S3STAT1 15 48 8 SCI3 Status Register 2 S3STAT2 15 50 9 SCI3 Interrupt Control Register SR3INT 15 52 15 2 5 Control Registers for SCI4 15 54 1 SCI4 Transmit Control Register ST4CON 15 54 2 SCI4 Receive Control Register SR4CON 15 56 3 SCI4 Transmi...

Page 12: ...INTCON1 16 17 7 A D Hard Select Register 0 ADHSEL0 16 19 8 A D Hard Select Register 1 ADHSEL1 16 22 9 A D Hard Select Software Control Register ADHSCON 16 25 10 A D Hard Select Enable Register ADHENCON 16 26 11 A D Result Registers ADCR0 ADCR23 16 28 16 3 Generated Timing of the A D Hard Select Mode 16 29 Chapter 17 Transition Detector Functions 17 1 Transition Detector Control Register TRNSCON 17...

Page 13: ...ity Control Register IPX0 IP00L IP00H IP10L IP10H IP20L IPX1 IP01L IP01H IP11L IP11H IP21L 20 7 20 3 Operation of Maskable Interrupt 20 8 Chapter 21 Bus Port Functions 21 1 Bus Port P0 P1 P12_0 P12_1 Functions 21 1 21 1 1 Operation of P0 P1 P12_0 and P12_1 During a Program Memory Access 21 1 21 2 External Memory Access 21 2 21 2 1 External Program Memory Access 21 2 21 2 2 External Program Memory ...

Page 14: ...onitor Function Operation 24 5 1 Setting the addresses 24 5 2 Detection of address matching 24 5 3 Reading data 24 5 Chapter 25 Electrical Characteristics MSM66591 Electrical Characteristics 25 1 25 1 Absolute Maximum Ratings 25 1 25 2 Operating Range 25 2 25 3 DC Characteristics 25 3 25 4 AC Characteristics 25 5 1 External Program Memory Control 25 5 25 5 A D Converter Characteristics 25 6 ML6659...

Page 15: ...Contents 12 ...

Page 16: ...Bit Timer Function 13 Chapter 13 PWM Functions 14 Chapter 14 Baud Rate Generator Functions 15 Chapter 15 Serial Port Functions 16 Chapter 16 A D Converter Functions 17 Chapter 17 Transition Detector Functions 18 Chapter 18 Peripheral Functions 19 Chapter 19 External Interrupt Request Function 20 Chapter 20 Interrupt Request Processing Function 21 Chapter 21 Bus Port Functions 22 Chapter 22 Expansi...

Page 17: ......

Page 18: ...Overview Chapter 1 1 ...

Page 19: ......

Page 20: ...eased by 2K bytes 1A00H to 21FFH Changed from 2000H to 3000H Increased by 64K bytes SEG2 One valid bit has been added to each of CSR and TSR Access forbidden to the internal SEG3 2000H 4000H 8000H 1 2 CLK 12 MHz 1 4 CLK 6 MHz 1 8 CLK 3 MHz 1 16 CLK 1 5 MHz 2 3 CLK 16 MHz 1 3 CLK 8 MHz 512 CLK 21 3 µs 384 CLK 16 µs 256 CLK 10 7 µs 1 4 CLK 6 MHz 1 8 CLK 3 MHz 1 16 CLK 1 5 MHz 512 CLK 18 3 µs 384 CLK...

Page 21: ...ressing Pointing register indirect addressing Stack addressing Immediate addressing 3 Minimum Instruction Cycle MSM66591 83 3 nsec 12 MHz internal 24 MHz ML66592 71 4 nsec 14 MHz internal 28 MHz 4 Program Memory ROM MSM66591 Internal 128K bytes External 128K bytes EA pin active ML66592 Internal 192K bytes External 256K bytes EA pin active 5 Data memory RAM MSM66591 Internal 6K bytes ML66592 Intern...

Page 22: ...with a 4 stage buffer on the receive side 4 UART synchronous type with BRG 1 Synchronous with 8 byte FIFO 1 12 A D Converter 10 bit resolution 24 channels 12 channel 2 13 Transition Detector 8 14 Watchdog Timer 1 15 Expansion Port serial parallel conversion 1 16 Interrupts Non maskable 1 Maskable internal 63 external 3 38 vectors 4 level priority 17 ROM Window Functions 18 RAM Monitor Functions 19...

Page 23: ...7 P6 P5 P4 P3 P2 P1 P0 OE Serial Port Serial Port with FIFO General Timer PWM A D Converter Port Cont RAM 6K bytes 2 Memory Cont Pointing Reg Local Reg SSP LRB PSW PC CSR TSR ALU ALU Cont ACC WDT ROM 128K bytes 1 Instruction Dec System Cont BUS Port Cont EA ALE P7_2 PSEN P7_3 AD0 P0_0 AD7 P0_7 A8 P1_0 A16 P12_0 A17 P12_1 3 RES OSC0 OSC1 SFTCLK P10_5 SFTDAT P10_6 SFTSTB P10_7 TRNS0 P4_0 TRNS7 P4_7 ...

Page 24: ... 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 144 143 142 141 140 139 138 137 136 135 134 133 132 131 130 129 128 127 126 125 124 123 122 121 120 119 118 117 116 115 114 113 112 111 110 109 P4_7 TRNS7 P4_6 TRNS6 P4_5 TRNS5 P4_4 TRNS4 P4_3 TRNS3 P4_2 TRNS2 P4_1 TRNS1 P4_0 TRNS0 P9_7 ECTCK P9_6 ETMCK P9_5 TXD4 P9_4 RXD4 P9_3 TXD3 P9_2 RXD3 P9_1 TXD2 P9_0 RXD2 GND V DD P3_7 CAP3 P3_6 CAP2 P3_5 CAP...

Page 25: ...ML66592 multiply the original oscillation clock by a factor of 2 to generate the master clock pulse CLK One master clock pulse CLK forms one state In other words one state is 41 7 nsec 12 MHz for the MSM66591 or 35 7 nsce 14 MHz for the ML66592 The execution of a single instruction is performed over several states S2 S3 Sn The number of states required for instruction execution depends upon the in...

Page 26: ...f LB A P3 instruction Execution of MOVB off N8 DP instruction DP 0024H LRB internal RAM area Execution of next instruction off N8 DP RAM P4 AL P3 Fetch of 2nd byte of LB A P3 instruction Fetch of MOVB off N8 DP instruction Fetch of LB A P3 instruction Fetch of 2nd byte of MOVB off N8 DP instruction Fetch of 3rd byte of MOVB off N8 DP instruction Fetch of next instruction Master clock CLK internal ...

Page 27: ... N8 instruction Execution of next instruction P4 N8 P3 AL Fetch of 2nd byte of STB A P3 instruction Fetch of MOVB P4 N8 instruction Fetch of STB A P3 instruction Fetch of 2nd byte of MOVB P4 N8 instruction Fetch of 3rd byte of MOVB P4 N8 instruction Fetch of next instruction Master clock CLK internal State PC internal P3 pin P4 pin OLD DATA NEW DATA AL value NEW DATA N8 value n 2 n 3 Fetch of 2nd ...

Page 28: ...e timing for the RUN bit that becomes 1 differs depending on the instruction executed The timing to read TM1 differs depending on the instruction executed The count timing of TM1 differs depending on the selected clock of TM1 m OLD DATA S2 S1 M1S1 Master clock CLK internal State TM1 count clock TM1RUN TM1 ACC m 1 m 2 m 3 m 4 m 5 m 6 m 4 DATA TMCON ACCL A TM1 TM1 Read ACCL 80H L A TM1 ...

Page 29: ...s 17 cycles if the program memory space is extended to 128K bytes IRQ is reset 0 at the 3rd cycle of the interrupt transition cycle S2 S1 M1S1 Master clock CLK internal State FFFC FFFD FFFE FFFF 0000 0001 0002 0003 Instruction A Instruction B Instruction C Interrupt transition cycle FFFD FFFE FFFF 0000 0001 0002 0003 0004 Instruction A Instruction B Interrupt transition cycle 0005 0004 TM1 count c...

Page 30: ...Description of Pins Chapter 2 2 ...

Page 31: ......

Page 32: ...ins of Port 1 I O can be specified in bit units by the Port 1 mode register P1IO By setting the EA pin to L leve P1_0 P1_7 also function as output pins for internal operations secondary function Description of Secondary Functions of Each Pin A8 A15 P1_0 P1_7 If the externally expanded data memory is accessed with the EA pin in L level these pins function as output pins to output addresses A8 A15 A...

Page 33: ...secondary function control register P3SF For the pins that have secondary functions set by P3SF I O settings by P3IO become invalid Description of Secondary Functions of Each Pin FTM17A P3_0 When register 17 TMR17 of the flexible timer is in RTO mode and when the value of the TMR17 matches the selected counter value the preset level is output When the TMR17 is in CAP mode FTM17A is set to input pi...

Page 34: ... 6 P5_0 P5_7 Input Output Pins 8 bit I O pins of Port 5 I O can be specified in bit units by the Port 5 mode register P5IO P5_0 P5_7 also function as output pins for internal operations secondary function Secondary functions for P5_0 P5_7 are set in bit units by the Port 5 secondary function control register P5SF For the pins that have secondary functions set by P5SF I O settings by P5IO become in...

Page 35: ...SF For pins that have secondary functions set by P6SF I O settings by P6IO become invalid Description of Secondary Functions of Each Pin INT0 P6_0 INT1 P6_1 Input pins for external interrupts 0 and 1 RXD1 P6_2 Input pin to input receive data at the serial port 1 receive side TXD1 P6_3 Output pin to output transmit data at the serial port 1 transmit side RXC1 P6_4 Configured to be the output pin fo...

Page 36: ...robe signal to externally latch the lower 8 bits of the address output from P0 If the EA pin has been set to a L level the pin function automatically changes to the secondary function If both the EA and RES pins have been set to a L level this pin is pulled up PSEN P7_3 When accessing external program memory this pin outputs a strobe signal for the read operation If the EA pin has been set to a L ...

Page 37: ...n pin 71 is in L level when P8 is in output status these pins output H or L level but if the OE pin is in H level these pins go into high impedance status 2 10 P9_0 P9_7 Input Output Pins 8 bit I O pins of Port 9 I O can be specified in bit units by the Port 9 mode register P9IO P9_0 P9_7 also functions as an output pin for internal operations secondary function Secondary functions for P9_0 P9_7 a...

Page 38: ...P10_7 are set in bit units by the Port 10 secondary function control register P10SF For the pins that have secondary functions set by P10SF I O settings by P10IO be come invalid Description of Secondary Functions of Each Pin RTO12 P10_0 RTO13 P10_1 The output pins from which the set level is output when the value of the registers 12 and 13 TMR12 TMR13 for the flexible timer is consistent with the ...

Page 39: ...l bits can be specified as input or output by the Port 11 mode register P11IO P11_0 P11_3 also function secondary and tertiary functions as I O pins for internal operation Description of Secondary Tertiary Functions of Each Pin RMRX P11_0 Address input pin for RAM monitor function Also functions tertiary function as data I O pin for serial write mode of the MSM66Q591 ML66Q592 flash EEPROM RMTX P11...

Page 40: ...17 that is used to access external expanded program memory ML66592 only 2 14 AI0 AI23 Input Pins Analog input pins of the A D converter 2 15 AVDD Input Pin Power input pin of the A D converter Supply the same voltage as VDD to this pin 2 16 VREF Input Pin Reference voltage input pin of the A D converter 2 17 AGND Input Pin GND pin of the A D converter 2 18 OSC0 OSC1 Input Pin Output Pin Connection...

Page 41: ...M66591 ML66592 mask ROM version 2 23 TEST Input Pin Load test pin Connect to GND In the MSM66Q591 ML66Q592 flash EEPROM version this pin becomes a high voltage supply pin while writing to the flash EEPROM In the MSM66591 ML66592 mask ROM version the RAM monitor function becomes enabled by setting the TEST pin to H level Do not apply a high voltage more than 5 V to this pin 2 24 VDD Input Pin Power...

Page 42: ...T DATA Hiz CONT Type 5 6 IN OUT During output VDD DATA Hiz CONT Type 3 During type 5 input Schmitt inverter input CMOS During type 6 input Schmitt inverter input TTL push pull output that can output high impedance Ø Ø Pin Name Type No Pin Name Type No P0_0 P0_7 6 P8_0 P8_7 5 P1_0 P1_7 5 P9_0 P9_7 5 P2_0 P2_7 5 P10_0 P10_7 5 P3_0 P3_7 5 P11_0 P11_7 5 P4_0 P4_7 5 P12_0 P12_1 5 P5_0 P5_7 5 AI0 AI23 3...

Page 43: ... Pin Recommended pin handling P0_0 P0_7 P1_0 P1_7 P2_0 P2_7 P3_0 P3_7 P4_0 P4_7 P5_0 P5_5 P6_0 P6_7 P7_0 P7_7 P8_0 P8_7 P9_0 P9_7 P10_0 P10_7 P11_0 P11_7 AI0 AI23 AVDD VREF AGND OE NMI EA For input setting H or L level For output setting open Connect to VREF or AGND Connect to GND Set to L level Set to H or L level Set to H level Connect to VDD P12_0 P12_1 TEST Set to L level ...

Page 44: ...CPU Architecture Chapter 3 3 ...

Page 45: ......

Page 46: ...ry model by setting the LROM bit bit 1 to 1 Write 0 to bit 0 To write to the LROM bit of MEMSCON first write 5H to the high order 4 bits low order 4 bits are arbitrary data of the memory size accepter MEMSACP allocated to the SFR area then write 0AH to them successively When an FJ or FCAL is executed with the LROM bit 0 an OP code trap is generated and a reset occurs When data is written to the LR...

Page 47: ... memory in 64K 65536 byte unit seg ment for segments 0 1 and 2 Since segment 3 is not provided do not try to access it However if more than 64K bytes segments 1 and 2 are accessed the LROM bit of the MEMSCON memory size control register allocated to SFR must be set to 1 The code segment register CSR specifies the segment to be used and the program counter PC specifies the address in the segment Ho...

Page 48: ... 0076H Vector table area 12 bytes Figure 3 1 a Memory Map of MSM66591 Program Memory Space Figure 3 1 b Memory Map of ML66592 Program Memory Space 17FFH 1800H FFFFH 0FFFH 1000H 0069H 006AH 0049H 004AH 0000H Vector table area 74 bytes VCAL table area 32 bytes ACAL area 2K bytes ACAL area 2K bytes 17FFH 1800H FFFFH 0FFFH 1000H 0000H Internal ROM area Segment 0 Segment 1 ACAL area 2K bytes 17FFH 1800...

Page 49: ...ates as a bus port In MSM66591 the internal program fetch enable area is 00000H 1FFFDH This means that the final address of instruction code must not exceed 1FFFDH The final address of the table data is 1FFFFH In ML66592 the internal program fetch enable area is 00000H 2FFFDH This means that the final address of instruction code must not exceed 2FFFDH The final address of the table data is 2FFFFH ...

Page 50: ...ble buffer RTO11 event generation 0028 Interrupt by SCI1 transmit receive 002A Interrupt by S0TM S1TM S2TM S3TM S4TM overflow 002C Interrupt by GTMC GEVC overflow 002E Interrupt by end of conversion by A D converter 1 in scan select hard select mode 0030 Interrupt by end of conversion by A D converter 0 in scan select hard select mode 0032 Interrupt by PWC0 PWC1 underflow or match 0034 Interrupt b...

Page 51: ...ss is significant data and program execution is started from the loaded address If however the program memory space is expanded to 128K bytes MSM66591 or 192K bytes ML66592 the SSP is decremented by 4 because the CSR value is saved at the same time that the PC is saved Also 0 is loaded to the CSR at the same time that the branch address content is loaded to the PC Therefore if the VCAL instruction...

Page 52: ...mory space for each segment 1000H 17FFH is an area that can directly call subroutines by a 2 byte call instruction ACAL Since the ACAL instruction can call subroutines in the current segment when an ACAL instruction is executed in segment 1 the ACAL area in segment 1 is called If an ACAL instruction is executed the next address of the next ACAL instruction is saved to the system stack the system s...

Page 53: ...4 bytes ML66592 53248 bytes The pointing register area PR 64 bytes and the special bit addressing area sbafix 64 bytes are located in the fixed page area In MSM66591 access to the area from 1A00H FFFFH is inhibited since it is not located in internal RAM However the ROM window setting area 2000H FFFFH can be accessed only if the ROM window has been set In ML66592 access to the area from 2200H FFFF...

Page 54: ...unction registers that the SFR area has are assigned to the 256 byte area of data memory space 0100H 01FFH 3 Internal RAM Area In the MSM66591 internal RAM is assigned to the 6K 6144 byte area of data memory space 0200H 19FFH In the ML66592 internal RAM is assigned to the 8K 8192 byte area of data memory space 0200H 21FFH Figure 3 2 b Memory Map of ML66592 Data Memory Space 0000H 00FFH 0100H 01FFH...

Page 55: ...signed to the 256 byte area of data memory space 0200H 02FFH a pointing register PR area and a special bit address area sbafix The pointing register area is assigned to 0200H 023FH and it has 8 sets of the follow ing 4 registers index registers X1 X2 data pointer DP user stack pointer USP All are 16 bit registers Even addresses are insignificant data and the following odd addresses are significant...

Page 56: ...FFFFH in the data memory space of the MSM66591 is not allocated as data memory However this area is used by the ROM window function if set by the ROM window setting register The 52K 53248 byte area from 3000H to FFFFH in the data memory space of the MSM66591 is not allocated as data memory However this area is used by the ROM window function if set by the ROM window setting register Corresponding ...

Page 57: ...ess in which the least significant bit LSB 0 even address becomes low order 8 bit data and 8 bit data indicated by an address in which LSB 1 odd address becomes high order 8 bit data 16 bit data where low order 8 bits are allocated in an odd address and high order 8 bits are allocated in an even address is inaccessible A boundary exists during word operation Such a boundary does not exists in the ...

Page 58: ... Segment register TSR 3 2 1 Arithmetic Register ACC The 16 bit arithmetic register is the accumulator ACC a central register for various operations If the transfer operation etc is Word type all 16 bits bits 15 0 are accessed Byte type the low order 8 bits bits 7 0 are accessed Nibble type the low order 4 bits bits 3 0 are accessed If the target bits are specified SBR RBR by ACC with a bit operati...

Page 59: ...o specify enable 1 or disable 0 of an entire maskable interrupt MIE flags that the user can freely use F0 2 flags available for future expansion of CPU core functions The user can freely use these flags in MSM66591 ML66592 BCB0 1 MAB PSW can be divided into PSWH bits 8 15 and PSWL bits 7 0 in 8 bit units and can perform 8 bit unit operations as well as 16 bit unit operations depending on the instr...

Page 60: ...zero flag is set to 1 if the value is zero as a result of an arithmetic instruction execution the loaded content is zero when a load instruction to ACC is executed the target bit is zero when a bit operation instruction is executed otherwise it is set to 0 A zero flag can be tested by a conditional branch instruction Bit 13 half carry flag HC A half carry flag is set to 1 if a carry or borrow from...

Page 61: ...lt of executing an arithmetic instruction exceeds the range expressed by a complement of 2 128 to 127 in the case of a byte operation 32768 to 32767 in the case of a word operation otherwise it is set to 0 Bit 8 master interrupt enable flag MIE A master interrupt enable flag controls enable 1 and disable 0 of an entire maskable interrupt This flag is set to 0 after it is saved to the system stack ...

Page 62: ...es not change even if an overflow occurs because of an increment in PC At reset when the RES signal is input the BRK instruction is executed the watchdog timer is overflown or an operation code trap is generated or when an interrupt occurs the content of the vector table area is loaded to the PC 3 Local Register Base LRB The LRB is a 16 bit register The low order 8 bits LRBL specifies 2K bytes of ...

Page 63: ...256 byte units The area of addresses 1A00H through 1FFFH is excluded 4 System Stack Pointer SSP SSP is a 16 bit register that indicates the stack address to save or return PC registers etc while handling an interrupt and executing CAL PUSH RT and POP instructions SSP is automatically incremented or decremented depending on the process to be executed A save or return to the stack address indicated ...

Page 64: ...ter USP PR is assigned to 0200H 023FH of the internal RAM area and one of the 8 sets is selected by SCB0 2 of PSWL If the PR function is not used PR can be used as internal RAM For all of X1 X2 DP and USP even addresses are low order 8 bits The following odd addresses are high order 8 bits USP DP X2 X1 USP X1 USP DP X2 X1 USP DP X2 X1 Pointing register set SCB 0 SCB 1 SCB 7 Expanded SFR area 01FFH...

Page 65: ... the local register base 1 byte of the specified 8 bytes is assigned as R by 3 bit data of a local register operation instruction 2 bytes are assigned as ER by 2 bit data ER0 R0 R1 ER1 R2 R3 ER2 R4 R5 ER3 R6 R7 ER0 R0 R1 0200H 0208H 0A00H R6 R7 LRBL 00H LRBL 01H LRBL FFH ER3 Specified in 8 byte units by LRBL 8 bits R0 to R7 are specified by 3 bits included in instruction code ER0 to ER3 are specif...

Page 66: ...pt No other methods can reload CSR Since in the MSM66591 CSR has only one valid bit while in the emulator for the MSM66591 CSR has two valid bits specify either segment 0 or segment 1 when executing the FJ or FCAL instruction for MSM66591 Since in the ML66592 segment 3 is not provided specify segment 0 1 or 2 when executing the FJ or FCAL instruction do not access segment 3 Each segment is assigne...

Page 67: ...n the MSM66591 TSR has only one valid bit while on the emulator for the MSM66591 TSR has two valid bits be sure to write 0s to bits 1 to 7 when writing to TSR In ML66592 only bits 0 and 1 of TSR are valid If a read instruction is executed 0s are read from bits 2 to 7 Since in the ML66592 segment 3 is not provided do not access segment 3 When writing to TSR be sure to write 0s to bits 2 to 7 Each s...

Page 68: ...FR function Abbreviated Abbreviation of name and data address symbol in assembler Name Specifically SSP LRB LRBL LRBH PSW PSWL and PSWH become ASSP ALRB ALRBL ALRBH APSW APSWL and APSWH respectively R W Read R write W possibility of SFR R W both read and write enable R read only W write only 8 16 Bit 8 bit operation 16 bit operation possibility of SFR Operation Specify a 16 bit operation for a 16 ...

Page 69: ...peration to a read only SFR B A read operation to a write only SFR C A 16 bit operation to an 8 bit operation only SFR D An 8 bit operation to a 16 bit operation only SFR E A 1 bit operation to a 16 bit operation only SFR F An operation to an address where register etc are not assigned G An operation to the emulator use area ...

Page 70: ... 5 Data Register Port 4 Data Register Port 3 Data Register Port 2 Data Register Port 1 Data Register Port 0 Data Register S1STAT S1BUF P3SF P2SF P11 P10 P9 P8 P7 P6 P5 P4 P3 P2 P1 P0 SCI0 Receive Buffer Register 1 Undefined SCI0 Transmit Receive Buffer Register 0 Undefined S0BUF2 S0BUF1 Port 9 Secondary Function Control Register 00 Port 8 Secondary Function Control Register 00 P9SF P8SF Port 10 Se...

Page 71: ...fer Register 3 Undefined Undefined S3BUF1 SCI3 Receive Buffer Register 3 SCI3 Receive Buffer Register 2 SCI3 Receive Buffer Register 1 PWC0 PWC0BF IE1 IRQ1 IRQ0 IE0 0030 Undefined S4BUF1 SCI4 Receive Buffer Register 1 00 01 S2STAT0 SR0INT SCI0 Interrupt Control Register SCI2 Status Register 0 00 S0STAT0 SCI0 Status Register 0 FFFF PWM Counter 0 PWC0 Buffer Register FFFF FFFF SCI3 Transmit Receive ...

Page 72: ...er Register PWR3 PW3BF PWM Register 4 PWR4 Buffer Register PWR4 PW4BF PWM Register 5 PWR5 Buffer Register PWR5 PW5BF PWM Register 6 PWR6 Buffer Register PWR6 PW6BF PWM Register 7 PWR7 Buffer Register PWR7 PW7BF PWM Register 8 PWR8 Buffer Register PWR8 PW8BF PWM Register 9 PWR9 Buffer Register PWR9 PW9BF PWM Register 10 PWR10 Buffer Register PWR10 PW10BF PWM Register 11 PWR11 Buffer Register PWR11 ...

Page 73: ...egister 10 Timer Register 11 Timer Register 12 Timer Register 13 Timer Register 14 Timer Register 15 Timer Register 16 Timer Register 17 R Address H Name Abbreviated Name BYTE R W 8 16 Bit Operation Reset State H Abbreviated Name WORD Addresses in the address column marked by indicate that the register has bits missing 0082 0083 0084 0085 0086 0087 0088 0089 008A 008B 008C 008D 008E 008F PWM Inter...

Page 74: ...CON12 RTO Control Register 12 F8 RTOCON13 RTO Control Register 13 F8 RTOCON16 RTO Control Register 16 F8 RTOCON17 RTO Control Register 17 00 RTO4CON 4 Port RTO Control Register 0F TM0L Timer Counter 0 Low Order 4 Bits 0000 0000 Timer Counter 1 TM1 8 Address H Name Abbreviated Name BYTE R W 8 16 Bit Operation Reset State H Abbreviated Name WORD Addresses in the address column marked by indicate tha...

Page 75: ...s in the address column marked by indicate that the register has bits missing 00D8 R 00D9 00DA 00DB 00DC 00DD 00DE 00DF Undefined 00E0 00E1 00E2 00E3 00E4 00E5 00E6 00E7 00E8 TMR0L TMR0 Low Order 4 Bits 00E9 00EA 00EB 00EC 00ED R W 3 00EE A D Result Register 0 00EF ADCR0 Undefined TMCON Timer Control Register EVNTCON2 Event Control Register 2 EVNTCONL Event Control Register L EVNTCONH Event Contro...

Page 76: ...the value of the PWM register PWRn is read When a write operation is performed data is written to the PWR buffer register PWnBF 3 Indicates that the R W operation of ADCR is a special operation ADCR is divided into the groups of ADCR0 2 4 6 8 10 ADCR1 3 5 7 9 11 ADCR12 14 16 18 20 22 and ADCR13 15 17 19 21 23 Data can be written simultaneously to each of these groups Writing to ADCR0 simultaneousl...

Page 77: ...rol Register R W 8 R W 8 00 P0IO Port 0 Mode Register 00 P1IO Port 1 Mode Register 00 P2IO Port 2 Mode Register 00 P3IO Port 3 Mode Register 00 P4IO Port 4 Mode Register 00 P5IO Port 5 Mode Register 00 P6IO Port 6 Mode Register 00 P7IO Port 7 Mode Register 00 P8IO Port 8 Mode Register 00 P9IO Port 9 Mode Register 00 P10IO Port 10 Mode Register 00 P11IO Port 11 Mode Register 00 P12IO Port 12 Mode R...

Page 78: ...er 8A ST4CON SCI4 Transmit Control Register 8 12 SR0CON SCI0 Receive Control Register 08 SR1CON SCI1 Receive Control Register 12 SR2CON SCI2 Receive Control Register 12 SR3CON SCI3 Receive Control Register 12 SR4CON SCI4 Receive Control Register R W 8 00 IP01L Interrupt Priority Register 01 IP01 00 IP01H 00 IP10L Interrupt Priority Register 10 IP10 00 IP10H 00 IP11L Interrupt Priority Register 11 ...

Page 79: ... Register 0000 TRNS Control Register TRNSCON R W 16 C0 EVDV0 Event Dividing Counter 0 C0 EVDV1 Event Dividing Counter 1 C0 EVDV2 Event Dividing Counter 2 C0 EVDV3 Event Dividing Counter 3 C0 EVDV14 Event Dividing Counter 14 C0 EVDV15 Event Dividing Counter 15 C0 EVDV0BF EVDV0 Buffer Register C0 EVDV1BF EVDV1 Buffer Register C0 EVDV2BF EVDV2 Buffer Register C0 EVDV3BF EVDV3 Buffer Register C0 EVDV1...

Page 80: ...CI4 Status Register 2 Address H Name Abbreviated Name BYTE R W 8 16 Bit Operation Reset State H Abbreviated Name WORD Addresses in the address column marked by indicate that the register has bits missing 0185 0186 0187 0188 0189 018A 018B 018C 018D 018E 018F 8 C0 SIO5CON1 SIO5 Control Register 1 00 SFADR Serial Address Output Register R W Undefined SFDIN Serial Data Input Register R Undefined SFDO...

Page 81: ...D bit 7 5 The flash control register area is used exclusively for the MSM66Q591 ML66Q592 Flash EEPROM version product For details refer to the MSM66Q591 Flash Memory User s Manual or ML66Q592 Flash Memory User s Manual 6 Do not access the emulator use area 01F1 01F0 01F2 01F3 01F4 01F5 01F6 01F7 01F8 01F9 01FA 01FB 01FC 01FD 01FE 01FF Flash Memory Control Register Area 5 Emulator Use Area 6 Addres...

Page 82: ...addressing formats Data in a table segment is read via the window on a data segment opened by a program See Chapter 5 Memory Control Functions 3 3 1 RAM Addressing RAM addressing modes specify addressing of program variables in RAM space Addressing modes provided are register addressing page addressing direct address ing pointing register indirect addressing and special bit area addressing Access ...

Page 83: ...te C carry flag Word Type FILL SSP MOV LRB 401H CLR PSW Byte Type CLRB PSWH INCB PSWL Bit Type MB C BITVAR C Pointing Register Addressing Pointing register contents are accessed Pointing registers are provided with eight sets of registers PR0 PR7 every 8 byte block in 200H 23FH in data memory but the set addressed in this mode is specified by the System Control Base SCB field in PSW X1 index regis...

Page 84: ...CLR USP Byte Type DJNZ X1L LOOP DJNZ X2L LOOP DJNZ DPL LOOP DJNZ USPL LOOP JRNZ DP LOOP D Local Register Addressing Local register contents are accessed Local registers are 256 sets of registers every 8 byte block in 200H 9FFH in data memory but the set addressed in this mode is specified by the Local Register Base LCB low order byte ER0 ER3 expanded local registers R0 R7 local registers Word Type...

Page 85: ...cifier The sfr can be omitted but then SFR page addressing will only be used when the assembler recognizes that an address is in the SFR page Every microcontroller device has its particular SFR symbols abbreviated names Normally these symbols are used for SFR accesses If an odd address is specified then the word data starting at the next lower even address will be accessed see Word Operation Howev...

Page 86: ...g FIXED page addressing specifies an offset in the FIXED page 200H 2FFH in data memory with one byte of instruction code Word byte or bit data can be accessed at the specified address The operand is coded with the fix addressing specifier The fix can be omitted but then FIXED page addressing will only be used when the assembler recognizes that an address is in the FIXED page If an odd address is s...

Page 87: ... address The operand is coded with the off addressing specifier The off can be replaced by but this will have a slightly different meaning when bit data in the SBA area is accessed see sbaoff Badr If an odd address is specified then the word data starting at the next lower even address will be accessed see Word Operation xx00H xxxxH xxFFH Current page xx00H xxxxH xxFFH Current page RAM xx00H xxxxH...

Page 88: ...nt physical segment of data memory address 0 0FFFFH 64K bytes with two bytes of instruction code excluding access inhibit area Word byte or bit data can be accessed at the specified address The operand is coded with the dir addressing specifier The dir can be omitted but then if an address in the SFR page or FIXED page is specified then the assembler may interpret it as SFR page addressing or FIXE...

Page 89: ... USP Indirect Addressing with 7 Bit Displacement n7 DP n7 USP E X1 X2 Indirect Addressing with 16 Bit Base D16 X1 D16 X2 F X1 Indirect Addressing with 8 Bit Register Displacement X1 R0 X1 A A DP X1 Indirect Addressing DP X1 indirect addressing specifies an address in the current physical segment ad dress 0 0FFFFH 64K bytes by the contents of a pointing register excluding access inhibit area Word b...

Page 90: ...nt specifies an address in the current physical segment address 0 0FFFFH 64K bytes by the contents of a pointing register exclud ing access inhibit area Word byte or bit data can be accessed at the specified address After access the pointing register contents will be incremented The increment will be 2 for word instructions and 1 for byte and bit instructions This mode is primarily used to access ...

Page 91: ...fies an address in the current physical segment of data memory address 0 0FFFFH 64K bytes by the contents of a pointing register excluding access inhibit area Word byte or bit data can be accessed at the specified address After access the pointing register contents will be decremented The decrement will be 2 for word instructions and 1 for byte and bit instructions This mode is primarily used to a...

Page 92: ...ontents of a pointing register as a base and adding a 7 bit displacement with sign embedded in instruction code bits 6 0 bit 6 is a signed bit excluding access inhibit area The range 64 to 63 bytes around the pointing register value can be accessed Word byte or bit data can be accessed at the specified address numeric_expression DP DP indirect addressing with 7 bit displacement numeric_expression ...

Page 93: ...address in the current physical segment address 0 0FFFFH 64K bytes Word 16 bit calculations are used to generate the address with overflows ignored Therefore the generated address will be 0 0FFFFH Word byte or bit data can be accessed at the specified address address_expression X1 X1 indirect addressing with 16 bit base address_expression X2 X2 indirect addressing with 16 bit base The address_expr...

Page 94: ...ddressing with 8 bit register displacement specifies an address in the current physical segment address 0 0FFFFH 64K bytes using the contents of a pointing register as a base and adding the contents of the Accumulator low byte AL or Local Register 0 R0 excluding access inhibit area Word 16 bit calculations are used to generate the address The 8 bit displacement obtained from the register will be e...

Page 95: ... A FIXED Page SBA Area Addressing sbafix Badr B Current Page SBA Area Addressing sbaoff Badr A FIXED Page SBA Area Addressing FIXED page SBA area addressing specifies a bit address in the FIXED page s 512 bit SBA area 2C0H 0 2FFH 7 Only bit data can be accessed at the specified address The instructions that can use this addressing are SB RB JBS and JBR B Current Page SBA Area Addressing Current pa...

Page 96: ...igned expressions For words that range is from 8000H to 0FFFFH and for bytes it is from 80H to 0FFH Word Type L A 1234H MOV X1 WORD_ARRAY_BASE Byte Type LB A 12H MOVB X1 BYTE_ARRAY_BASE 2 Table Data Addressing Table data addressing specifies access for the 64K bytes in the table segment of ROM space as specified by TSR This mode can be used with operands of LC LCB CMPC and CMPCB instructions A Dir...

Page 97: ...tructions LC LCB CMPC and CMPCB Word Type LC A A CMPC A 1234 X1 Byte Type LCB A ER0 CMPCB A VAR C RAM Addressing Indirect Addressing with 16 Bit Base RAM addressing indirect addressing with 16 bit base specifies two bytes D16 in instruction code as a base and adds it to the contents of word data specified by RAM addressing to obtain an address 0 0FFFFH 64K bytes in the table segment specified by T...

Page 98: ...ssing can be used with J and CAL instructions Example of Use J 3000H CAL LABEL B FAR Code Addressing Far code addressing specifies an address 0 0 1 0FFFFH 128K bytes in program memory space with three bytes of instruction code This addressing can be used with FJ and FCAL instructions Example of Use FJ 1 3000H FCAL FARLABEL C Relative Code Addressing Relative code addressing takes the current progr...

Page 99: ...with 4 bits of instruction code The vector table is located at even ad dresses in the range 004AH 0069H in segment 0 This addressing can be used only with VCAL instructions Example of Use VACL 4AH VCAL 0 4AH VCAL VECTOR F RAM Addressing Indirect Code Addressing RAM addressing indirect code addressing uses word data specified by RAM addressing as a pointer to the code segment Word 16 bit calculatio...

Page 100: ...le data in ROM space using RAM addressing This mode reads data in the table segment specified by TSR using data segment window opened by the program See ROM Window Function Data memory addressing is permitted in the ROM window area but results are not guaranteed if an instruction that writes to the ROM window is executed ...

Page 101: ...3 56 MSM66591 ML66592User sManual Chapter 3 CPU Architecture ...

Page 102: ...CPU Control Functions Chapter 4 4 ...

Page 103: ......

Page 104: ...tion The MSM66591 ML66592 standby function has two types of operation modes HALT mode stops the clock supply CPU by software STOP mode stops the original oscillation clock supply by software Each mode is set by Stop code acceptor for STPACP STOP mode Standby control register for SBYCON HALT and STOP modes Table 4 1 lists the standby modes indicating the output pin status etc in standby mode ...

Page 105: ... impedance No change P7_2 P7_3 primary function No change High impedance No change P7_3 secondary function PSEN H level High impedance H level P7_2 secondary function ALE L level High impedance L level TBC Operating Stop WDT Operating Stop FTM Operating Stop GTMC GEVC Operating Operating if external clock is selected 3 S0TM S4TM Operating Stop SCI0 SCI5 Operating Stop ADC Operating Stop PWM Stop O...

Page 106: ...through current will not flow into the input circuits of pins in high impedance status even if the pin becomes open externally The through current prevention circuit however does not operate for external interrupt pins INT0 INT2 and for the clock input pins of event timers ETMCK ECTCK since they can be the factors that clear STOP mode Therefore through current may flow into the input circuits of e...

Page 107: ... by a non maskable interrupt HALT mode is cleared unconditionally and the CPU executes a non maskable interrupt process A maskable interrupt clears HALT mode if both an interrupt request flag IRQ bit and an interrupt enable flag IE bit are 1 After HALT mode is cleared the maskable interrupt process is executed if the master interrupt enable flag MIE of PSW is 1 If the master interrupt enable flag ...

Page 108: ...t are 1 After STOP mode is cleared the maskable interrupt process is executed if the master interrupt enable flag MIE of PSW is 1 If the master interrupt enable flag MIE of PSW is 0 the instruction next to the instruction that set STOP mode instruction that set STP bit 0 of SBYCON to 1 is executed However if in a non maskable interrupt routine STOP mode is set and then cleared by an interrupt requ...

Page 109: ...ES pin input apply L level until more than 1 ms has elapsed after the original oscillation clock is stable The reset process has priority over all other processes interrupt process instruction execution Since all other processes are suspended the content of registers and RAM at this time are not guaranteed Figure 4 3 shows the reset pin connection example Table 4 2 shows the output pin status at r...

Page 110: ..._0 P7_1 P7_4 P7_7 P8 P11 P12_0 P12_1 Status Hiz Hiz H level pull up Hiz Hiz RES VDD Reset Processing Circuit SW and R are needed for manual reset VDD Di R SW C External Internal Notes 1 If the EA pin is at a L level and external memory is selected P7_2 P7_3 P0 P1 P12_0 and P12_1 ML66592 only will automatically take their secondary functions and go into an operating state 2 Hiz refers to the high i...

Page 111: ...4 8 MSM66591 ML66592User sManual Chapter 4 CPU Control Functions ...

Page 112: ...Memory Control Functions Chapter 5 5 ...

Page 113: ......

Page 114: ...a at the same address in the segment in the program memory space specified by TSR is accessed read To the instruction execution cycle 3 cycles are added by one access reading in the case of a byte instruction and 6 cycles are added in the case of a word instruction If a write instruction is executed when the ROM window function is valid the result is not guaranteed Cycles are not added in this cas...

Page 115: ...nd the ROM window function is disabled ROMWIN can be written only once after reset A second or later writing is ignored This means that once a ROM window function is set it cannot be changed until reset ROMWIN however can be read any number of times Note In MSM66591 do not write any other value than 2H 4H and 8H to the low order 4 bits of ROMWIN In ML66592 do not write any other value than 3H 4H a...

Page 116: ...order 6 bits Figure 5 2 shows the configuration of ROMRDY At reset when the RES signal is input the BRK instruction is executed the watchdog timer is overflown or an operation code trap is generated both RAMRDY and ROMRDY becomes FFH Then if the external program memory is accessed 3 cycles of a wait cycle can be inserted Note In the MSM66591 ML66592 unlike internal program memory access when exter...

Page 117: ...5 4 MSM66591 ML66592User sManual Chapter 5 Memory Control Functions ...

Page 118: ...Port Functions Chapter 6 6 ...

Page 119: ......

Page 120: ...on Type A Has secondary functions as an address data bus and automatically switches to its secondary function when the external memory is accessed Goes into high impedance status if the output status of the OE pin is in H level Type B Has secondary functions and switches to its secondary function according to the status of the port secondary function control register Goes into high impedance statu...

Page 121: ...serial 1 transmission TXC1 I O P6_6 C 1 I O Serial port 0 data input RXD0 Input P6_7 C 1 I O Serial port 0 data output TXD0 Output Port 7 P7_0 P7_1 D 2 I O None P5_7 C 1 I O Wait signal input pin WAIT Input P5_6 C 1 I O Clockout CLKOUT Output P7_4 P7_7 B 4 I O PWM output PWM0 PWM3 Output Port 8 P8_0 P8_7 B 8 I O PWM output PWM4 PWM11 Output Port 9 P7_3 C 1 I O External program memory access PSEN O...

Page 122: ...t no P10_6 C 1 I O Expansion port data I O SFTDAT I O no P10_7 C 1 I O Latch strobe output for expansion port SFTSTB Output no Port 11 P11_0 C 1 I O Address input for RAM monitor function RMRX Input no P11_4 P11_7 D 4 I O None Port 12 P12_0 A 1 I O External program memory address A16 Output no yes P12_1 1 E 1 I O None yes P11_3 C 1 I O Address match detect output RMACK Output no Data I O for writi...

Page 123: ...s output pins and data I O pins for external program memory access The pin specified as the output goes into high impedance if OE is in H level In the ML66592 P12_1 also is a Type A port Figure 6 1 shows the configuration of a Type A port Figure 6 1 Configuration of Type A D A C PmIOn Pm_n Pmn in OE pin External Memory Control signals D data A address C secondary function control signals Pm_n m 0 ...

Page 124: ... ports act as secondary function input and output pins according to the specification of the secondary function control register PmSFn The pin specified as the output goes into high impedance if OE is in H level Figure 6 2 shows the configuration of a Type B port C PmIOn OE pin Secondary function control signals C secondary function control signal O secondary function output data Pm_n m 2 n 0 7 m ...

Page 125: ... L level Then when external program memory is accessed P7_3 func tions as an output pin PSEN pin for a strobe signal to be output for a read operation and P7_2 functions as an output pin ALE pin for a strobe signal used to externally latch the low order 8 bits of addresses that are output from P0 Figure 6 3 shows the configuration of a Type C port Figure 6 3 Configuration of Type C C PmIOn Seconda...

Page 126: ...Type D ports Figure 6 5 Configuration of Type E 6 1 5 Configuration of Type E P12_1 Type E ports function as I O pins without secondary functions When the OE pin is in H level the pin specified as the output goes into high impedance The ML66592 has no Type E ports Figure 6 5 shows the configuration of Type E port Pm_n m 7 n 0 1 m 11 n 4 7 Internal Bus PmIOn Read Control Pm_n Pmn in Pm_n m 12 n 1 I...

Page 127: ... by the bit symbol corresponding to each bit Bit symbols for bits of a port data register are for example P0_0 for bit 0 and P0_1 for bit 1 in Port 0 So a port data register is represented correspending to each bit either by the bit symbol such as P0_0 or P0_1 or by the dot operator such as P0 0 or P0 1 in assembly language 6 2 2 Port Mode Register PnIO n 0 12 A port mode register PnIO n 0 12 is a...

Page 128: ...en the RES signal is input the BRK instruction is executed the watchdog timer is overflown or an operation code trap is generated If each bit of PnSF is set to 0 primary function is selected and if 1 secondary function is selected Ports 0 1 and 12 have no secondary function control register since the primary secondary function of these ports is automatically selected by hard ware ...

Page 129: ...ister 0020 P6SF 00 Port 7 Secondary Function Control Register P7SF 00 Port 8 Secondary Function Control Register 0022 P8SF 00 Port 9 Secondary Function Control Register 0023 P9SF 00 Port 10 Secondary Function Control Register 0024 P10SF 00 Port 12 Data Register 0025 P12 00 Port 0 Mode Register P0IO 00 Port 1 Mode Register P1IO 00 Port 2 Mode Register 0112 P2IO 00 Port 3 Mode Register 0113 P3IO 00 ...

Page 130: ...ration code trap is generated Port 0 goes into high impedance input port P0IO 00H The content of P0 becomes 00H P0_7 P0_6 P0_5 P0_4 P0_3 P0_2 P0_1 P0_0 7 6 5 4 3 2 1 0 P0 P0IO7 P0IO6 P0IO5 P0IO4 P0IO3 P0IO2 P0IO1 P0IO0 7 6 5 4 3 2 1 0 P0IO P0_n input 0 P0_n output 1 n 0 7 6 3 Port 0 P0 Port 0 P0_0 P0_7 is an 8 bit I O port Input or output can be specified for each bit by the Port 0 mode register P...

Page 131: ...1IO If a read instruction is executed to P1 in which input is specified P1IOn 0 by P1IO the content of the pin is read If a read instruction is executed to P1 in which output is specified P1IOn 0 the content of the port data register is read If an arithmetic instruction increment instruction or instruction of that type read modify write instruc tion is executed to P1 the content of the pin or port...

Page 132: ...igure 6 8 shows the configuration of the Port 2 data register P2 the Port 2 mode register P2IO and the Port 2 secondary function control register P2SF P2_7 P2_6 P2_5 P2_4 P2_3 P2_2 P2_1 P2_0 7 6 5 4 3 2 1 0 P2 P2IO7 P2IO6 P2IO5 P2IO4 P2IO3 P2IO2 P2IO1 P2IO0 7 6 5 4 3 2 1 0 P2IO P2_n input 0 P2_n output 1 n 0 7 RTO11 RTO10 RTO9 RTO8 RTO7 RTO6 RTO5 RTO4 7 6 5 4 3 2 1 0 P2SF P2_0 0 Flexible timer rea...

Page 133: ...ted to P2 the content of the pin or port data register is read according to specification by P2IO when reading and data is written to the port data register when writing At reset when the RES signal is input the BRK instruction is executed the watchdog timer is overflown or an operation code trap is generated Port 2 becomes a high impedance input port P2IO 00H P2SF 00H The content of P2 becomes 00...

Page 134: ...e register P3IO and the Port 3 secondary function control register P3SF Figure 6 9 Configuration of P3 P3IO and P3SF P3_7 P3_6 P3_5 P3_4 P3_3 P3_2 P3_1 P3_0 7 6 5 4 3 2 1 0 P3 P3IO7 P3IO6 P3IO5 P3IO4 P3IO3 P3IO2 P3IO1 P3IO0 7 6 5 4 3 2 1 0 P3IO P3_n input 0 P3_n output 1 n 0 7 CAP3 CAP2 CAP1 CAP0 FTM17D FTM17C FTM17B FTM17A 7 6 5 4 3 2 1 0 P3SF P3_0 0 Flexible timer I O 17A 1 P3_1 0 Flexible timer...

Page 135: ...rding to specification by P3IO when reading and data is written to the port data register when writing At reset when the RES signal is input the BRK instruction is executed the watchdog timer is overflown or an operation code trap is generated Port 3 becomes a high impedance input port P3IO P3SF 00H The content of P3 becomes 00H Table 6 4 Read of P3 P3_0 P3_1 P3_3 P3IO P3SF Read Data 0 0 Pin 1 0 O...

Page 136: ...P4 the Port 4 mode register P4IO and the Port 4 secondary function control register P4SF Figure 6 10 Configuration of P4 P4IO and P4SF P4_7 P4_6 P4_5 P4_4 P4_3 P4_2 P4_1 P4_0 7 6 5 4 3 2 1 0 P4 P4IO7 P4IO6 P4IO5 P4IO4 P4IO3 P4IO2 P4IO1 P4IO0 7 6 5 4 3 2 1 0 P4IO P4_n input 0 P4_n output 1 n 0 7 TRNS7 TRNS6 TRNS5 TRNS4 TRNS3 TRNS2 TRNS1 TRNS0 7 6 5 4 3 2 1 0 P4SF P4_0 0 Transition detector 0 input ...

Page 137: ...xecuted to Port 4 the content of the pin or port data register is read according to specification by P4IO when reading and data is written to the port data register when writing At reset when the RES signal is input the BRK instruction is executed the watchdog timer is overflown or an operation code trap is generated Port 4 becomes a high impedance input port P4IO P4SF 00H The content of P4 become...

Page 138: ...3 P5_2 P5_1 P5_0 7 6 5 4 3 2 1 0 P5 P5IO7 P5IO6 P5IO5 P5IO4 P5IO3 P5IO2 P5IO1 P5IO0 7 6 5 4 3 2 1 0 P5IO P5_n input 0 P5_n output 1 n 0 7 6 8 Port 5 P5 Port 5 P5_0 P5_7 is a 8 bit I O port Input or output can be specified for each bit by the Port 5 mode register P5IO In addition to the port function a secondary function serial interface with FIFO is assigned to Port 5 Port function secondary funct...

Page 139: ... arithmetic instruction increment instruction or instruction of that type read modify write instruction is executed to P5 the content of the pin or port data register is read according to specification by P5IO when reading and data is written to the port data register when writing At reset when the RES signal is input the BRK instruction is executed the watchdog timer is overflown or an operation ...

Page 140: ...egister P6IO and the Port 6 secondary function control register P6SF Figure 6 12 Configuration of P6 P6IO and P6SF P6_7 P6_6 P6_5 P6_4 P6_3 P6_2 P6_1 P6_0 7 6 5 4 3 2 1 0 P6 P6IO7 P6IO6 P6IO5 P6IO4 P6IO3 P6IO2 P6IO1 P6IO0 7 6 5 4 3 2 1 0 P6IO P6_n input 0 P6_n output 1 n 0 7 TXD0 RXD0 TXC1 RXC1 TXD1 RXD1 INT1 INT0 7 6 5 4 3 2 1 0 P6SF P6_0 0 External interrupt 0 input 1 P6_1 0 External interrupt 1...

Page 141: ...d to P6 according to the content of P6I0 and P6SF If an arithmetic instruction increment instruction or instruction of that type read modify write instruction is executed to Port 6 the content of the pin or port data register is read according to specification by P6IO when reading and data is written to the port data register when writing At reset when the RES signal is input the BRK instruction i...

Page 142: ... 8 bit I O port Input or output can be specified for each bit by the Port 7 mode register P7IO In addition to the port function a secondary function output of the strobe signal for the external memory etc is assigned to Port 7 Port function secondary function is selected by the Port 7 secondary function control register P7SF When the EA pin is set to L level P7_2 and P7_3 automatically operates as...

Page 143: ...r port data register is read according to specification by P7IO when reading and data is written to the port data register when writing At reset when the RES signal is input the BRK instruction is executed the watchdog timer is overflown or an operation code trap is generated Port 7 becomes a high impedance input port P7IO P7SF 00H The content of P7 becomes 00H Table 6 7 Read of P7 P7_0 P7_3 P7_4 ...

Page 144: ...el But if the OE pin pin 71 is in H level Port 8 goes into high impedance status Figure 6 14 shows the configuration of the Port 8 data register P8 the Port 8 mode register P8IO and the Port 8 secondary function control register P8SF Figure 6 14 Configuration of P8 P8IO and P8SF P8_7 P8_6 P8_5 P8_4 P8_3 P8_2 P8_1 P8_0 7 6 5 4 3 2 1 0 P8 P8IO7 P8IO6 P8IO5 P8IO4 P8IO3 P8IO2 P8IO1 P8IO0 7 6 5 4 3 2 1...

Page 145: ...ted to P8 the content of the pin or port data register is read according to specification by P8IO when reading and data is written to the port data register when writing At reset when the RES signal is input the BRK instruction is executed the watchdog timer is overflown or an operation code trap is generated Port 8 becomes a high impedance input port P8IO 00H P8SF 00H The content of P8 becomes 00...

Page 146: ... secondary function control register P9SF Figure 6 15 Configuration of P9 P9IO and P9SF P9_7 P9_6 P9_5 P9_4 P9_3 P9_2 P9_1 P9_0 7 6 5 4 3 2 1 0 P9 P9IO7 P9IO6 P9IO5 P9IO4 P9IO3 P9IO2 P9IO1 P9IO0 7 6 5 4 3 2 1 0 P9IO P9_n input 0 P9_n output 1 n 0 7 P9SF 7 6 5 4 3 2 1 0 ECTCK ETMCK TXD4 RXD4 TXD3 RXD3 TXD2 RXD2 0 P9_0 1 Serial port 2 receive data input 0 P9_1 1 Serial port 2 transmit data output 0 ...

Page 147: ...n arithmetic instruction increment instruction or instruction of that type read modify write instruction is executed to P9 the content of the pin or port data register is read according to specification by P9IO when reading and data is written to the port data register when writing At reset when the RES signal is input the BRK instruction is executed the watchdog timer is overflown or an operation...

Page 148: ...high impedance status Figure 6 16 shows the configuration of the Port 10 data register P10 the Port 10 mode register P10IO and the Port 10 secondary function control register P10SF Figure 6 16 Configuration of P10 P10IO and P10SF P10_7 P10_6 P10_5 P10_4 P10_3 P10_2 P10_1 P10_0 7 6 5 4 3 2 1 0 P10 P10IO7 P10IO6 P10IO5 P10IO4 P10IO3 P10IO2 P10IO1 P10IO0 7 6 5 4 3 2 1 0 P10IO P10_n input 0 P10_n outp...

Page 149: ...he port data register when writing At reset when the RES signal is input the BRK instruction is executed the watchdog timer is overflown or an operation code trap is generated Port 10 becomes a high impedance input port P10IO P10SF 00H The content of P10 becomes 00H Table 6 9 Read of P10 indicates either 1 or 0 P10_0 P10_1 P10_5 P10_7 P10_4 P10IO 1 0 P10SF 0 1 0 1 0 P10_6 Read Data Pin Output latc...

Page 150: ... 0 P11_n output 1 n 0 7 Figure 6 17 Configuration of P11 and P11IO If a read instruction is executed to P11 in which the input is specified P11IOn 0 by P11IO the content of the pin is read If a read instruction is executed to P11 in which the output is specified P11IOn 1 the content of the port data register is read If an arithmetic instruction increment instruction or instruction of that type rea...

Page 151: ...12 mode register P12IO Figure 6 18 Configuration of P12 and P12IO If a read instruction is executed to P12 in which input is specified P12IOn 0 by P12IO the content of the pin is read If a read instruction is executed to P12 in which output is specified P12IOn 0 the content of the port data register is read If an arithmetic instruction increment instruction or instruction of that type read modify ...

Page 152: ...Output Pin Control Pin OE Chapter 7 7 ...

Page 153: ......

Page 154: ... P2 P3_0 P3_3 P7_4 P7_7 P8 P10_0 P10_4 P12_0 and P12_1 are configured to function as output pins each pin goes into high impedance status and if the OE pin is in L level each pin outputs L or H level When P0 P1 P2 P3_0 P3_3 P7_4 P7_7 P8 P10_0 P10_4 P12_0 and P12_1 are specified to input each pin functions as an input pin regardless of the status of the OE pin The level of the OE pin can be read by...

Page 155: ...7 2 MSM66591 ML66592User sManual Chapter 7 Output Pin Control Pin OE ...

Page 156: ...Clock Generation Circuit Chapter 8 8 ...

Page 157: ......

Page 158: ...onnection example for external clock input Figure 8 1 An Example of a Crystal Oscillation Circuit Connection Figure 8 2 Connection Example for External Clock Input Oscillation Circuit Clock pulse control circuit Master clock pulse CLK Internal to MSM66591 ML66592 External to MSM66591 ML66592 OSC0 OSC1 STOP signal OST1 0 External clock Open 2x Clock Circuit Notes 1 The C0 and C1 values must be set ...

Page 159: ...red by an interrupt request the master clock pulse is transferred when the number of clocks specified by OST0 and OST1 bits 4 and 5 of SBYCON have elapsed after oscillation starts If STOP mode is cleared by the RES pin input the setting of OST0 and OST1 by SBYCON is invalid therefore apply L level to the RES pin until at least 1 ms has elapsed after the original oscillation clock stabilizes ...

Page 160: ...Time Base Counter TBC Chapter 9 9 ...

Page 161: ......

Page 162: ...operation code trap is gener ated and from then on operates unless the supply of the original oscillation clock stops Figure 9 1 shows the configuration of TBC Figure 9 1 Configuration of TBC 1 CLK in the above figure used for TM0 and TM1 is supplied to the timer data sequencer and to the timing controller of each timer register module 2 If the 1 n 4 bit counter is set as n 1 and if the TBCCLK is ...

Page 163: ...s F0H TBCKDVR TBCKDVR is a 4 bit register that stores reload values into TBCKDVC Write is valid but write to high order 4 bits is invalid Read is valid but the high order 4 bits will read 1 if read At reset when the RES signal is input the BRK instruction is executed the watchdog timer is overflown or an operation code trap is generated TBCKDVR becomes F0H At reset the 1 n counter divides the 1 CL...

Page 164: ...Watchdog Timer WDT Chapter 10 10 ...

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Page 166: ...K or 1 512 TBCCLK Figure 10 1 Configuration of WDTCON 10 2 Operation of WDT 1 256 TBCCLK or 1 512 TBCCLK can be selected for the WDT input clock by the WDTSEL bit bit 0 of the WDT control register WDTCON The WDT stops its function at reset when the RES signal is input the BRK instruction is executed the WDT is overflown and an operation code trap is generated The WDT is started by writing 3CH to W...

Page 167: ...tWDT 1 f µsec n 28 occurs since the content of TBC does not change When the master clock of the MSM66591 is 24 MHz and n 8 the result is tWDT 43 69 msec tWDT 85 33 µsec When the master clock of the ML66592 is 28 MHz and n 8 the result is tWDT 37 45 msec tWDT 73 14 µsec 10 4 Program Runaway Detection Timing Diagram Figure 10 3 a shows an example of timing when a program is executed normally Figure ...

Page 168: ... Content of WDT 3CH write WDT start C3H write WDT clear to 0 3CH write WDT clear to 0 C3H write WDT clear to 0 within tWDT within tWDT within tWDT a When program is executed normally Content of WDT 3CH write WDT start C3H write WDT clear to 0 Overflow occurred Reset by WDT tWDT b When program runaway occurs OVF 000H OVF 000H t t Progress of Program ...

Page 169: ...No writing to WDT Progress of program during an abnormal execution Progress of program during a normal execution WDT is cleared to 0 by writing 3CH to WDT WDT is cleared to 0 by writing C3H to WDT WDT is cleared to 0 by writing 3CH to WDT WDT is cleared to 0 by writing C3H to WDT WDT is cleared to 0 by writing 3CH to WDT WDT is cleared to 0 by writing C3H to WDT ...

Page 170: ...Flexible Timer FTM Chapter 11 11 11 ...

Page 171: ......

Page 172: ... fourteen 16 bit registers control registers and other components The functions of the timer include 20 bit capture modes 4 type A1 16 bit capture modes 2 type A2 double buffer real time output modes 10 type B capture real time output mode with 4 port RTO 1 type D capture real time output mode 1 type E Figure 11 1 shows the configuration of FTM Table 11 1 shows the list of SFRs for controlling FTM...

Page 173: ...t TM0 20 bit TM1 16 bit TMCON 8 bit Counter Selection Part TMSEL 16 bit TMSEL2 8 bit Type A1 Register Modules TMR0 TMR3 TMRL0 TMRL3 CAPCON EVDV0 EVDV3 EVDV0BF EVDV3BF EVNTCONL EVNTCONH Type A2 Register Modules TMR14 TMR15 CAPCON RTOCON14 RTOCON15 EVNTCON2 Type D Register Module TMR17 TMRMODE RTOCON17 RTO4CON CAPCON Type B Register Modules TMR4 TMR13 TMR4BF TMR13BF RTOCON4 RTOCON13 P10_4 FTM16 Type...

Page 174: ... 5 Timer Register 6 Timer Register 7 Timer Register 8 Timer Register 9 Timer Register 10 Timer Register 11 Timer Register 12 Timer Register 13 Timer Register 14 Timer Register 15 Timer Register 16 Timer Register 17 TMR4 Buffer Register TMR5 Buffer Register TMR6 Buffer Register TMR7 Buffer Register TMR1 TMR2 TMR3 TMR4 TMR5 TMR6 TMR7 TMR8 TMR9 TMR10 TMR11 TMR12 TMR13 TMR14 TMR15 TMR16 TMR17 TMR4BF T...

Page 175: ...rol Register 13 RTO Control Register 16 Timer Counter 0 Timer Counter 1 TMR0 Low order 4 Bits TMR1 Low order 4 Bits TMR2 Low order 4 Bits TMR3 Low order 4 Bits TMSEL2 RTOCON4 RTOCON5 RTOCON6 RTOCON7 RTOCON8 RTOCON9 RTOCON10 RTOCON11 RTOCON12 RTOCON13 RTOCON16 TMSEL TMR13BF 0000 0000 FC F8 F8 F8 F8 F8 F8 F8 F8 F8 F8 F8 RTOCON17 TM0L TM0 TM1 0000 TMR0L Undefined TMR1L Undefined TMR2L Undefined TMR3L...

Page 176: ... EVDV15 C0 EVDV0BF C0 EVDV1BF C0 EVDV3BF C0 EVDV14BF C0 EVDV15BF C0 8 R W Event Dividing Counter 14 EVDV2 Buffer Register EVDV15 Buffer Register EVDV2BF EVDV14 C0 C0 017C 017D 017E CAPCON Capture Control Register TMR Mode Register TMRMODE F2 8 16 0000 R W Some addresses are not consecutive Addresses in the address column marked by indicate that the register has bits missing 00DC 00DD 00DE 00DF Tim...

Page 177: ...imer 0 is a 20 bit counter the low order 4 bits are TM0L and the high order 16 bits are TM0 and can be read written by the program However if TM0 is read the con tents of TM0L are latched to the temporary register at the same time If TM0L is read after that the latched contents are read Therefore if the data of Timer 0 is read in 20 bit length read TM0 first then TM0L If TM0L is written the low or...

Page 178: ... 16 TBCCLK 1 0 1 1 32 TBCCLK 1 1 0 1 64 TBCCLK 1 1 1 1 128 TBCCLK TM1RUN TM1CK2 TM1CK1 TM1CK0 TM0RUN TM0CK2 TM0CK1 TM0CK0 7 6 5 4 3 2 1 0 TMCON Figure 11 3 Configuration of TMCON TM0 TM1 TM0 TM1 TM0 TM1 TM0 CLK TMDS TMD Figure 11 4 Output of Timer Data Sequencer The 4 bit output TM0L4 of TM0L is connected to the timer register module type A1 The high order 16 bit output of TM0 and the 16 bit outpu...

Page 179: ...egister 0 TMR0 through timer register 3 TMR3 consist of 20 bits TM0L4 is always connected to the low order 4 bits regardless of the specifica tion of TMSEL 1s are read from bits 7 2 when TMSEL2 is read Note that bit manipulation instructions such as SB and RB cannot be used because TMSEL has only 16 bit access At reset when the RES signal is input the BRK instruction is executed the watchdog timer...

Page 180: ... TMSEL Figure 11 6 Configuration of TMSEL2 15 14 13 12 11 10 9 8 0 TMR8 is connected to TM0 1 TMR8 is connected to TM1 0 TMR9 is connected to TM0 1 TMR9 is connected to TM1 0 TMR10 is connected to TM0 1 TMR10 is connected to TM1 0 TMR11 is connected to TM0 1 TMR11 is connected to TM1 0 TMR12 is connected to TM0 1 TMR12 is connected to TM1 0 TMR13 is connected to TM0 1 TMR13 is connected to TM1 TMS...

Page 181: ...unction control register to 1 Figure 17 1 shows the configuration of type A1 register module Figure 11 7 Configuration of Type A1 Register Module 1 Timer Registers TMR0 TMR0L TMR3 TMR3L The timer register consists of 20 bits that are divided into high order 16 bits TMR0 TMR3 and low order 4 bits TMR0L TMR3L The counter specified by TMSEL is connected to TMR0 TMR3 and the low order 4 bits of the 20...

Page 182: ... CAP3 P3_7 pins Since CAPCON has only 16 bit access bit manipulation instructions such as SB and RB cannot be used At reset when the RES signal is input the BRK instruction is executed the watchdog timer is overflown or an operation code trap is generated CAPCON becomes 0000H and CAP0 CAP3 CAP14 CAP15 FTM16 and FTM17A are specified to the falling edge Figure 11 8 shows the configuration of bits 0 ...

Page 183: ...nd a 1 1 division is specified Figure 11 9 shows the configuration of EVNTCONL and Figure 11 10 the configuration of EVNTCONH T1EV2 T1EV1 T1EV0 T0EV2 T0EV1 T0EV0 T0EV Dividing ratio of valid edge of CAP0 pin 2 1 0 0 0 0 1 1 division 0 0 1 1 2 division 0 1 0 1 4 division 0 1 1 1 8 division 1 0 0 1 16 division 1 0 1 1 32 division 1 1 1 64 division 7 6 5 4 3 2 1 0 T1EV Dividing ratio of valid edge of...

Page 184: ... 8 division 1 0 0 1 16 division 1 0 1 1 32 division 1 1 1 64 division 7 6 5 4 3 2 1 0 T3EV Dividing ratio of valid edge of CAP3 pin 2 1 0 0 0 0 1 1 division 0 0 1 1 2 division 0 1 0 1 4 division 0 1 1 1 8 division 1 0 0 1 16 division 1 0 1 1 32 division 1 1 1 64 division EVNTCONH indicates a bit that is not provided 1 is read if a read instruction is executed indicates either 1 or 0 Figure 11 10 C...

Page 185: ...r Registers EVDV0BF EVDV3BF EVDV0BF EVDV3BF are 6 bit registers that hold the content of EVDV0 EVDV3 content just prior to being cleared to 0 when a capture event is generated Figure 11 12 shows the configuration of EVDVnBF n 0 3 Figure 11 12 Configuration of EVDVnBF n 0 3 Write to EVDV0BF EVDV3BF is valid however write to the high order 2 bits is invalid Read is valid however 1 is read from the h...

Page 186: ... only once even if the capture event is input twice or more at an interval of less than 3 CLKs Figure 11 13 a and b shows capture operation timing examples Figure 11 13 a Capture Operation Timing Example Figure 11 13 b Capture Operation Timing Example a b c d e a b c d e Interrupt request is generated Interrupt request is generated Interrupt request is generated Interrupt request is generated Inte...

Page 187: ...apture pin EVDVn counts their number If the counter value and the dividing value specified by EVNTCONL or EVNTCONH match a capture event is generated If a capture event is generated a capture interrupt request is generated the counter value is loaded to the timer register the EVDVn value is loaded to EVDVnBF and EVDVn is cleared to 0 n 0 3 3 Operation to Switch Dividing Ratio Since the dividing ra...

Page 188: ... used as a capture function set the bit corresponding to the Port 10 secondary function control register to 1 Figure 11 14 shows the configuration of a type A2 register module Figure 11 14 Configuration of Type A2 Register Module 1 Timer Registers TMR14 TMR15 The timer registers consist of 16 bits The counter specified by TMSEL is connected to TMR14 and TMR15 If the specified valid edge is input t...

Page 189: ...not be used At reset when the RES signal is input the BRK instruction is executed the watchdog timer is overflown or an operation code trap is generated CAPCON becomes 0000H and CAP0 CAP3 CAP14 CAP15 FTM16 and FTM17A are specified to the falling edge Figure 11 15 shows the configuration of bits 8 15 of CAPCON Figure 11 15 Configuration of Bits 8 15 of CAPCON 14 13 12 11 10 9 8 7 Bit Valid edge of ...

Page 190: ...s 88H and a 1 1 division is specified Figure 11 16 shows the configuration of EVNTCON2 Figure 11 16 Configuration of EVNTCON2 T15EV2 T15EV1 T15EV0 T14EV2 T14EV1 T14EV0 T14EV Dividing ratio of valid edge of CAP14 pin 2 1 0 0 0 0 1 1 division 0 0 1 1 2 division 0 1 0 1 4 division 0 1 1 1 8 division 1 0 0 1 16 division 1 0 1 1 32 division 1 1 1 64 division 7 6 5 4 3 2 1 0 T15EV Dividing ratio of vali...

Page 191: ... EVDV14 and EVDV15 become C0H 5 EVDV14 EVDV15 Buffer Registers EVDV14BF EVDV15BF EVDV14BF and EVDV15BF are 6 bit registers that hold the content of EVDV14 and EVDV15 content just prior to being cleared to 0 when a capture event is generated Figure 11 18 shows the configuration of EVDVnBF n 14 15 Figure 11 18 Configuration of EVDVnBF n 14 15 Write to EVDV14BF and EVDV15BF is valid however write to ...

Page 192: ...ted Interrupt request is generated 11 4 2 Operation of Type A2 Register Modules TMR14 TMR15 If the valid edge specified by CAPCON is input to CAP14 or CAP15 pin when the TM specified by TMSEL is in RUN status the divider divides the pulse in the dividing ratio specified by EVNTCON2 In that case an interrupt request by a capture event is generated and at the same time the content of the counter spe...

Page 193: ...ng value specified by EVNTCON2 match a capture event is generated If a capture event is generated a capture interrupt request is generated the counter value is loaded to the timer register the EVDVn value is loaded to EVDVnBF and EVDVn is cleared to 0 n 14 15 3 Operation to Switch Dividing Ratio Since the dividing ratio is programmable the dividing operation may differ depending on the timing that...

Page 194: ...registers TMR4 TMR13 TMR4BF TMR13BF pins to output signals by the real time output function RTO4 RTO13 a timing controller a comparator to compare timer counter and timer register values and control registers RTOCON4 RTOCON13 to control real time output operations If RTO4 RTO13 pins are used for real time output functions set the corresponding bit of the Port 2 and Port 10 secondary function contr...

Page 195: ...he watchdog timer is overflown or an operation code trap is generated TMR4BF TMR13BF become 0000H 3 Real time Output Control Registers RTOCON4 RTOCON13 A real time output control register RTOCON4 RTOCON13 consists of 3 bits If TMR4 TMR13 and the counter values specified by TMSEL match the content of TnBF0 bit 1 is loaded to TnOUT bit 0 and the content of TnBF1 bit 2 is loaded to TnBF0 bit 1 Set to...

Page 196: ... The content of this flag is output to an RTOn pin If the selected counter value and the TMRn value match the content of this flag is loaded to TnOUT If the selected counter value and the TMRn value match the content of this flag is loaded to TnBF0 indicates a bit that is not provided 1 is read if a read instruction is executed n 4 13 RTOCON4 RTOCON13 ...

Page 197: ...herefore set the time for the next event to TMR4 TMR13 and set the time for the event after the next event to TMR4BF TMR13BF Set the state for the next event to TnBF0 and set the state for the event after the next event to TnBF1 Then a one shot pulse output can be controlled at one time Figure 11 22 shows a type B register module operation example If RTO4 RTO13 pins are used for real time output f...

Page 198: ...s FTM17A FTM17D to either input capture signals or output signals by the real time output function a timing controller a comparison circuit to compare timer counter and timer register values a control register TMRMODE to specify the operation of the type D register module and control registers RTOCON17 RTO4CON CAPCON to control the operation of the type D register module Figure 11 23 shows the con...

Page 199: ...TM TMD T17BF0 FTM17B Timing Controller 17 CLK T17SEL TMDS Comparison Circuit TMR17 T17OUT Interrupt request T17CER TMD CAP17 T17BFA T17OUTA T17BFB T17OUTB T17BFD T17OUTD T17BFC T17OUTC FTM17C FTM17D CAP17 FTM17A Figure 11 23 Configuration of Type D Register Module ...

Page 200: ...t the state for the next event to TnBF0 4 port real time output register RTO4CON consists of 8 bits When TMR17 is in 4 port RTO mode if TMR17 matches the counter value specified by TMSEL2 the content of T17BFA bit 4 T17BFD bit 7 is loaded to T17OUTA bit 0 T17OUTD bit 3 Set the state for the next event to T17BFA T17BFD RTOCON17 and RTO4CON can be read written by the program Write to RTOCON17 is val...

Page 201: ...flag is loaded to T17OUT When TMR17 is in CAP mode if the selected counter completes one cycle during a capture event the content of this flag is 1 if not 0 indicates a bit that is not provided 1 is read if a read instruction is executed RTOCON17 T17BFD T17BFC T17BFB T17BFA T17OUTDT17OUTCT17OUTBT17OUTA 7 6 5 4 3 2 1 0 When TMR17 is in 4 port RTO mode the content of this flag is output to FTM17D FT...

Page 202: ...d the watchdog timer is overflown or an operation code trap is generated TMRMODE becomes F2H TMR16 is specified to RTO mode and TMR17 is specified to 4 port output RTO mode Figure 11 26 shows the configuration of TMRMODE 7 6 5 4 3 2 1 0 T17MD1 T17MD0 T16MD0 TMR16 Function 0 1 RTO mode CAP mode T17MD TMR17 Function 1 0 0 0 0 1 1 4 port RTO mode CAP mode RTO mode indicates a bit that is not provided...

Page 203: ...ause CAPCON has only 16 bit access At reset when the RES signal is input the BRK instruction is executed the watchdog timer is overflown or an operation code trap is generated CAPCON becomes 0000H and CAP0 CAP3 CAP14 CAP15 TMR16 and TMR17A are specified to falling edge Figure 11 27 shows the configuration of bits 8 15 of CAPCON Figure 11 27 Configuration of Bits 8 15 of CAPCON 14 13 12 11 10 9 8 7...

Page 204: ... 0 Therefore set to TMR17 the time for the next event and set to T17BF0 the state for the next event The RTO4CON function becomes invalid Figure 11 28 shows an example of a type D register module operation in RTO mode If FTM17A pin is used as RTO function the bit corresponding to the Port 3 secondary function control register must be set to 1 In this case RTO4CON becomes invalid Figure 11 28 Examp...

Page 205: ... TMR17 T17BFA T17BFD Interrupt request is generated Write to TMR17 T17BFA T17BFD 2 Operation in 4 Port Output Real time Output Mode 4 Port RTO When the TM specified by TMSEL2 is in RUN status TMR17 is constantly compared with the specified counter value and if they match an interrupt request by a real time output is generated and the contents of T17BFA T17BFD bits 4 7 of RTO4CON are loaded to T17O...

Page 206: ...t remains at 0 if the cycle is not completed when the capture value is less than or equal to the last capture value The cycle flag is set to 1 at the timing of the next capture operation after the above mentioned condition is met Note that when capture operations are not performed the cycle flag is not set even if the counter cycle is completed Figure 11 30 shows a capture operation timing example...

Page 207: ...a timing controller a comparison circuit to compare timer counter and timer register values a control register TMRMODE to specify the operation of a type E register module and control registers RTOCON16 CAPCON to control the operation of the type E register module Figure 11 31 shows the configuration of a register module type E If FTM16 pin is used for real time output or for capture functions set...

Page 208: ...F0 RTOCON16 can be read written by the program Write is valid however write to high order 5 bits is invalid Read is valid however 1 is always read from the high order 5 bits If a read modify write instruction such as SB RB and XORB is executed to RTOCON16 just prior to an event generated by RTO T16BF0 and T16OUT may not operate normally At reset when the RES signal is input the BRK instruction is ...

Page 209: ...watchdog timer is overflown or an operation code trap is generated TMRMODE becomes F2H TMR16 is specified to RTO mode and TMR17 is specified to 4 port output RTO mode Figure 11 33 shows the configuration of TMRMODE 7 6 5 4 3 2 1 0 T17MD1 T17MD0 T16MD0 Function of TMR16 0 1 RTO mode CAP mode T17MD Function of TMR17 1 0 0 0 0 1 1 4 port RTO mode CAP mode RTO mode indicates a bit that is not provided...

Page 210: ...be used because CAPCON has only 16 bit access At reset when the RES signal is input the BRK instruction is executed the watchdog timer is overflown or an operation code trap is generated CAPCON becomes 0000H and CAP0 CAP3 CAP14 CAP15 TMR16 and TMR17A are specified to falling edge Figure 11 34 shows the configuration of bits 8 15 of CAPCON Figure 11 34 Configuration of Bits 8 15 of CAPCON 15 14 13 ...

Page 211: ...module type D See Figure 11 28 If FTM16 pin is used for RTO functions set the corresponding bit of the Port 10 second ary function control register to 1 2 Operation in CAP Mode When the TM specified by TMSEL2 is in RUN status if the valid edge specified by CAPCON is input to FTM16 pin an interrupt request by a capture event is generated and at the same time the content counter specified by TMSEL2 ...

Page 212: ...h signal of TM1 and TMRn becomes H level while the content of TM1 is 100H TMRn and the RTO output pin change at the fall of the match signal and by the AND signal of the TM1 clock pulse The corresponding interrupt request flag is set at the latter half of M1S1 signal to indicate the beginning of an instruction Figure 11 35 Example of Type B Register Module Output Timing Changes 100H 101H 102H 100H...

Page 213: ...11 42 MSM66591 ML66592User sManual Chapter 11 Flexible Timer FTM ...

Page 214: ...General Purpose 8 Bit Timer Function Chapter 12 12 ...

Page 215: ......

Page 216: ... GTM Control SFRs Address H Name Abbreviated Name BYTE R W 8 16 Bit Operation 8 Reset State H 016A General Purpose 8 Bit Timer Control Register GTMCON 30 016B General Purpose 8 Bit Event Counter GEVC 00 016C General Purpose 8 Bit Timer Counter GTMC 00 016D General Purpose 8 Bit Timer Register GTMR 00 Abbreviated Name WORD Addresses in the address column marked by indicate that the register has bit...

Page 217: ...ck P9_6 ETMCK pin at that time 12 1 General Purpose 8 Bit Timer GTM The general purpose 8 bit timer consists of an 8 bit timer counter GTMC an 8 bit timer register GTMR that stores the reload values of GTMC and a general purpose 8 bit timer control register GTMCON that controls operations Figure 12 1 shows the configuration of GTM General purpose 8 bit timer interrupts and general purpose 8 bit ev...

Page 218: ...ter and its content is loaded to GTMC when a GTMC overflow occurs At reset when the RES signal is input the BRK instruction is executed the watchdog timer is overflown or an operation code trap is generated GTMR becomes 00H 3 General Purpose 8 Bit Timer Control Register GTMCON GTMCON is an 8 bit register that selects the count clock of GTMC and controls the start stop of the count operation using ...

Page 219: ... 1 4 TBCCLK 0 1 0 1 8 TBCCLK 0 1 1 1 16 TBCCLK 1 0 0 1 64 TBCCLK 1 0 1 1 256 TBCCLK 1 1 0 External rise P9_6 ETMCK pin 1 1 1 External fall P9_6 ETMCK pin 0 GTMC count operation stop 1 GTMC count runs 0 GEVC count clock external rise P9_7 ECTCK pin 1 GEVC count clock external fall P9_7 ECTCK pin 0 GEVC count operation stop 1 GEVC count runs indicates a bit that is not provided 1 is read if a read i...

Page 220: ...imer GTMC When this bit is 0 no interrupt request has been generated When 1 an interrupt request has been generated EEVC bit 2 EEVC enables or disables the generation of interrupt requests by the general purpose 8 bit event counter GEVC When this bit is 0 interrupts are disabled When 1 interrupts are enabled QEVC bit 3 QEVC indicates whether an interrupt request has been generated by the general p...

Page 221: ... GEVC The GEVC is an 8 bit counter that generates an interrupt request when an overflow occurs The count clock of the GEVC is selected by the high order 2 bits of the general purpose 8 bit timer control register GTMCON At reset when the RES signal is input the BRK instruction is executed the watchdog timer is overflown or an operation code trap is generated the GEVC becomes 00H and the count opera...

Page 222: ...he generation of interrupt requests by the gen eral purpose 8 bit timer GTMC When this bit is 0 interrupts are disabled When 1 interrupts are enabled QGTM bit 1 QGTM indicates whether an interrupt request has been generated by the general purpose 8 bit timer GTMC When this bit is 0 no interrupt request has been generated When 1 an interrupt request has been generated EEVC bit 2 EEVC enables or dis...

Page 223: ...12 8 MSM66591 ML66592User sManual Chapter 12 General Purpose 8 Bit Timer Function ...

Page 224: ...PWM Functions Chapter 13 13 ...

Page 225: ......

Page 226: ...z a 10 6 msec valid bit length 8 bits to 838 9 msec valid bit length 16 bits cycle can be selected by combining the input clock of the PWM counter and a valid bit length Figure 13 1 shows the configuration of PWM Table 13 1 lists the PWM control SFRs Figure 13 1 Configuration of PWM CLK master clock Interrupt TBCCLK PWCnBF Comparator PWnBF PWRn Active Controller To port Sele ctor PWCn R S Q Q Outp...

Page 227: ...WR3 Buffer Register PWM Register 4 PWR4 Buffer Register PWM Register 5 PWR5 Buffer Register 0052 PWM Register 6 PWR6 Buffer Register PWM Register 7 PWR7 Buffer Register PWM Register 8 PWR8 Buffer Register PWM Register 9 PWR9 Buffer Register PWM Register 10 PWR10 Buffer Register PWM Register 11 PWR11 Buffer Register PWC0 PWC0BF PWC1 PWC1BF PWC2 PWC2BF PWC3 PWC3BF PWC4 PWC4BF PWC5 PWC5BF PWC6 PWC6BF...

Page 228: ...gister 2 PWM Control Register 4 0082 PWRUNL PWINTQ0L PWINTQ1L PWINTE0L PWINTE1L PWCON0 PWCON2 PWCON4 PWRUN PWINTQ0 PWINTQ1 PWINTE0 PWINTE1 PWM Control Register 1 PWM Control Register 3 PWM Control Register 5 PWCON1 PWCON3 PWCON5 PWRUNH PWINTQ0H PWINTQ1H PWINTE0H PWINTE1H R W 8 8 16 00 00 00 00 00 00 00 00 00 00 00 F0 F0 F0 F0 F0 Some addresses are not consecutive Addresses in the address column ma...

Page 229: ...ter generates an interrupt request PWC0 and PWC1 PWC2 and PWC3 PWC4 and PWC5 PWC6 and PWC7 PWC8 and PWC9 PWC10 and PWC11 are common and the contents of the 16 bit PWM counter buffer register are loaded to the PWM counters The PWM counter then loads the content of the 16 bit PWM buffer register to the 16 bit PWM register and sets the output F F to 1 PWC0 PWC11 can be read but cannot be written by t...

Page 230: ...ly compares the content of PWC0 PWC11 and that of PWR0 PWR11 when the corresponding PWnRUN bit is 1 It generates an interrupt request PWM0 and PWM1 PWM2 and PWM3 PWM4 and PWM5 PWM6 and PWM7 PWM8 and PWM9 PWM10 and PWM11 are common and resets the output F F if contents of PWC0 PWC11 and PWR0 PWR11 match 6 Output F F The output F F is set to 1 when the corresponding PWnRUN bit is set to 1 and when P...

Page 231: ... TBCCLK 0 1 2 TBCCLK 1 1 4 TBCCLK 0 1 8 TBCCLK 1 1 16 TBCCLK 1 0 0 1 1 2 0 0 0 0 1 1 PWM1 high active status PWM1 low active status 0 1 PWCON0 indicates either 1 or 0 PW3ACTPW3CK2PW3CK1PW3CK0PW2ACTPW2CK2PW2CK1PW2CK0 7 6 5 4 3 2 1 0 PW2CK Count Clock of PWC2 0 0 Master clock 1 TBCCLK 0 1 2 TBCCLK 1 1 4 TBCCLK 0 1 8 TBCCLK 1 1 16 TBCCLK 1 0 0 1 1 2 0 0 0 0 1 1 PWM2 high active status PWM2 low active...

Page 232: ...BCCLK 1 1 4 TBCCLK 0 1 8 TBCCLK 1 0 0 1 1 2 0 0 0 0 1 PWM5 high active status PWM5 low active status 0 1 PWCON2 1 1 16 TBCCLK 1 1 1 16 TBCCLK 1 indicates either 1 or 0 PW7ACTPW7CK2PW7CK1PW7CK0PW6ACTPW6CK2PW6CK1PW6CK0 7 6 5 4 3 2 1 0 PW6CK Count Clock of PWC6 0 0 Master clock 1 TBCCLK 0 1 2 TBCCLK 1 1 4 TBCCLK 0 1 8 TBCCLK 1 1 16 TBCCLK 1 0 0 1 1 2 0 0 0 0 1 1 PWM6 high active status PWM6 low activ...

Page 233: ... 4 TBCCLK 0 1 8 TBCCLK 1 0 0 1 1 2 0 0 0 0 1 PWM9 high active status PWM9 low active status 0 1 PWCON4 1 1 16 TBCCLK 1 1 1 16 TBCCLK 1 indicates either 1 or 0 PW11ACTPW11CK2PW11CK1PW11CK0PW10ACTPW10CK2PW10CK1PW10CK0 7 6 5 4 3 2 1 0 PW10CK Count Clock of PWC10 0 0 Master clock 1 TBCCLK 0 1 2 TBCCLK 1 1 4 TBCCLK 0 1 8 TBCCLK 1 1 16 TBCCLK 1 0 0 1 1 2 0 0 0 0 1 1 PWM10 high active status PWM10 low ac...

Page 234: ...WRUNH become 00H and F0H respectively and PWC0 PWC11 stop the count operation Figure 13 8 Configuration of PWRUNL PW7RUNPW6RUNPW5RUNPW4RUNPW3RUNPW2RUNPW1RUNPW0RUN 7 6 5 4 3 2 1 0 0 PWC0 stops 1 PWC0 runs 0 PWC1 stops 1 PWC1 runs 0 PWC2 stops 1 PWC2 runs 0 PWC3 stops 1 PWC3 runs 0 PWC6 stops 1 PWC6 runs 0 1 0 PWC4 stops 1 PWC4 runs 0 PWC5 stops 1 PWC5 runs PWC7 stops PWC7 runs PWRUNL Figure 13 9 Co...

Page 235: ...Q1 are flags individual interrupt request flags that are set to 1 if the contents of PWC0 PWC11 and PWR0 PWR11 match The bits of PWINTQ0 and PWINTQ1 do not become 0 automatically even if a corresponding interrupt occurs Therefore it is necessary to reset them to 0 by the program If an underflow of PWC0 PWC11 and a match of the content of PWC0 PWC11 and that of PWR0 PWR11 occur concurrently when PW...

Page 236: ...es 0 PWC6 underflow generation no 1 PWC6 underflow generation yes 0 1 0 PWC4 underflow generation no 1 PWC4 underflow generation yes 0 PWC5 underflow generation no 1 PWC5 underflow generation yes PWC7 underflow generation no PWC7 underflow generation yes PWINTQ0L QPW11 QPW10 QPW9 QPW8 7 6 5 4 3 2 1 0 0 PWC8 underflow generation no 1 PWC8 underflow generation yes 0 PWC9 underflow generation no 1 PW...

Page 237: ...no 1 Match of PWC6 and PWR6 yes 0 1 0 Match of PWC4 and PWR4 no 1 Match of PWC4 and PWR4 yes 0 Match of PWC5 and PWR5 no 1 Match of PWC5 and PWR5 yes Match of PWC7 and PWR7 no Match of PWC7 and PWR7 yes PWINTQ1L Figure 13 13 Configuration of PWINTQ1H QPWR11 QPWR10 QPWR9 QPWR8 7 6 5 4 3 2 1 0 0 Match of PWC8 and PWR8 no 1 Match of PWC8 and PWR8 yes 0 Match of PWC9 and PWR9 no 1 Match of PWC9 and PW...

Page 238: ...1 undferflow generation PWINTE1 is a register that controls enable disable of the interrupt request by matching of the contents of PWC0 PWC11 and PWR0 PWR11 Figure 13 14 shows the configuration of PWINTE0L Figure 13 15 the configuration of PWINTE0H Figure 13 16 the configuration of PWINTE1L and Figure 13 17 the configuration of PWINTE1H At reset when the RES signal is input the BRK instruction is ...

Page 239: ... request by PWC6 underflow enabled 0 1 0 Interrupt request by PWC4 underflow disabled 1 Interrupt request by PWC4 underflow enabled 0 Interrupt request by PWC5 underflow disabled 1 Interrupt request by PWC5 underflow enabled Interrupt request by PWC7 underflow disabled Interrupt request by PWC7 underflow enabled PWINTE0L EPW11 EPW10 EPW9 EPW8 7 6 5 4 3 2 1 0 0 Interrupt request by PWC8 underflow d...

Page 240: ...uest by match of PWC4 and PWR4 disabled 1 Interrupt request by match of PWC4 and PWR4 enabled 0 Interrupt request by match of PWC5 and PWR5 disabled 1 Interrupt request by match of PWC5 and PWR5 enabled Interrupt request by match of PWC7 and PWR7 disabled Interrupt request by match of PWC7 and PWR7 enabled PWINTE1L Figure 13 17 Configuration of PWINTE1H EPWR11 EPWR10 EPWR9 EPWR8 7 6 5 4 3 2 1 0 0 ...

Page 241: ...of the contents of PWC0 PWC11 and PWR0 PWR11 occur concurrently when PWR 0000H is set the interrupt request by an underflow of PWC0 PWC11 is given priority Therefore only the individual interrupt request flag by the underflow of PWC0 PWC11 is set to 1 the individual interrupt request flag by the match of the contents of PWC0 PWC11 and PWR0 PWR11 is not set to 1 The duty immediately after PWM start...

Page 242: ...ck of PWM TBCCLK dividing ratio of the 1 n counter 1 4 PWCnBF value 00FFH f PWM 24 000 000 1 4 1 255 1 93 750 Hz 10 67 µsec Figure 13 18 shows an example of PWM output operation Figure 13 19 shows an example of a PWM output timing change Content of PWC PWR value PWnRUN bit PWM output waveform FFFFH 0H UDF PWnRUN bit is set n 0 11 PWC PWR interrupt req is generated PWC underflow is generated interr...

Page 243: ... Chapter 13 PWM Functions Figure 13 19 PWM Output Timing Change Example 100H 0FFH 0FEH PWC clock TBCCLK dividing ratio of the 1 n counter 1 4 Master clock CLK Content of PWC Match signal of PWC and PWR Change of PWM output pin MIS1 IRQ ...

Page 244: ...Baud Rate Generator Functions Chapter 14 14 ...

Page 245: ......

Page 246: ...ame except for the address of registers located in the SFR area Interrupts for S0TM S1TM S2TM S3TM and S4TM are assigned to the same interrupt vector The generation of individual interrupt requests are enabled or disabled by bit 3 ESTMn of each timer control register SnCON Verification of whether an interrupt request has been generated is performed based on bit 2 QSTMn of each timer control regist...

Page 247: ...mer SCI4 Timer SCI0 Timer Control Register SCI1 Timer Control Register SCI2 Timer Control Register SCI3 Timer Control Register SCI4 Timer Control Register S0CON S1CON S2CON S3CON S4CON S1TM S2TM S3TM S4TM 0000 0000 0000 0000 02 02 02 02 02 8 Some addresses are not consecutive Addresses in the address column marked by indicate that the register has bits missing Address H Name Abbreviated Name BYTE ...

Page 248: ...RK instruction is executed the watchdog timer is overflown or an operation code trap is generated S0TM becomes 0000H and the count operation stops 3 SCI0 Timer Control Register S0CON S0CON is an 8 bit register The high order 4 bits bits 4 7 select the count clock of S0TM and controls the start stop of the count operation The low order 2 bits bits 2 and 3 perform interrupt related controls The leas...

Page 249: ... mode 1 S0TM baud rate generator mode for SCI0 0 SCI0 timer counter overflow generation no 1 SCI0 timer counter overflow generation yes 0 SCI0 timer counter count operation STOP 1 SCI0 timer counter count operation RUN S0CK Count Clock of S0TM 2 1 0 0 0 0 Master clock CLK 0 0 1 1 2 CLK 0 1 0 1 2 TBCCLK 0 1 1 1 4 TBCCLK 1 0 0 1 8 TBCCLK 1 0 1 1 16 TBCCLK 1 1 0 1 64 TBCCLK 1 1 1 1 256 TBCCLK indicat...

Page 250: ...rflow is generated The calculation of the baud rate when SCI0 is used as the baud rate generator is shown below B baud rate f BRG S0TM count clock frequency Hz D reload value 0 to 255 Even if the reload value is written to the SCI0 timer register the content of the SCI0 timer counter does not change If the SCI0 timer is used as the auto reload timer baud rate generator from the beginning of an ope...

Page 251: ...instruction is executed the watchdog timer is overflown or an operation code trap is generated S1TM becomes 0000H and the count operation stops 3 SCI1 Timer Control Register S1CON S1CON is an 8 bit register The high order 4 bits bits 4 7 select the count clock of S1TM and control the start stop of the count operation The low order 2 bits bits 2 3 perform interrupt related controls The least signif...

Page 252: ...er mode 1 S1TM baud rate generator mode for SCI1 0 SCI1 timer counter overflow generation no 1 SCI1 timer counter overflow generation yes 0 SCI1 timer counter count operation STOP 1 SCI1 timer counter count operation RUN S1CK Count Clock of S1TM 2 1 0 0 0 0 Master clock CLK 0 0 1 1 2 CLK 0 1 0 1 2 TBCCLK 0 1 1 1 4 TBCCLK 1 0 0 1 8 TBCCLK 1 0 1 1 16 TBCCLK 1 1 0 1 64 TBCCLK 1 1 1 1 256 TBCCLK indic...

Page 253: ...aud rate generator is shown below UART mode B baud rate f BRG S1TM count clock frequency Hz D reload value 0 to 255 Synchronous mode B baud rate f BRG S1TM count clock frequency Hz D reload value 0 to 255 Even if the reload value is written to the SCI1 timer register the content of the SCI1 timer counter does not change If the SCI1 timer is used as the auto reload timer baud rate generator from th...

Page 254: ...ruction is executed the watchdog timer is overflown or an operation code trap is generated S2TM becomes 0000H and the count operation stops 3 SCI2 Timer Control Register S2CON S2CON is an 8 bit register The high order 4 bits bits 4 7 select the count clock of S2TM and controls the start stop of the count operation The low order 2 bits bits 2 and 3 perform interrupt related controls The least signi...

Page 255: ...r mode 1 S2TM baud rate generator mode for SCI2 0 SCI2 timer counter overflow generation no 1 SCI2 timer counter overflow generation yes 0 SCI2 timer counter count operation STOP 1 SCI2 timer counter count operation RUN S2CK Count Clock of S2TM 2 1 0 0 0 0 Master clock CLK 0 0 1 1 2 CLK 0 1 0 1 2 TBCCLK 0 1 1 1 4 TBCCLK 1 0 0 1 8 TBCCLK 1 0 1 1 16 TBCCLK 1 1 0 1 64 TBCCLK 1 1 1 1 256 TBCCLK indica...

Page 256: ...low is generated The calculation of the baud rate when SCI2 is used as the baud rate generator is shown below B baud rate f BRG S2TM count clock frequency Hz D reload value 0 to 255 Even if the reload value is written to the SCI2 timer register the content of the SCI2 timer counter does not change If the SCI2 timer is used as the auto reload timer baud rate generator from the beginning of an opera...

Page 257: ...uction is executed the watchdog timer is overflown or an operation code trap is generated S3TM becomes 0000H and the count operation stops 3 SCI3 Timer Control Register S3CON S3CON is an 8 bit register The high order 4 bits bits 4 7 select the count clock of S3TM and controls the start stop of the count operation The low order 2 bits bits 2 and 3 perform interrupt related controls The least signif...

Page 258: ...er mode 1 S3TM baud rate generator mode for SCI3 0 SCI3 timer counter overflow generation no 1 SCI3 timer counter overflow generation yes 0 SCI3 timer counter count operation STOP 1 SCI3 timer counter count operation RUN S3CK Count Clock of S3TM 2 1 0 0 0 0 Master clock CLK 0 0 1 1 2 CLK 0 1 0 1 2 TBCCLK 0 1 1 1 4 TBCCLK 1 0 0 1 8 TBCCLK 1 0 1 1 16 TBCCLK 1 1 0 1 64 TBCCLK 1 1 1 1 256 TBCCLK indic...

Page 259: ...w is generated The calculation of the baud rate when SCI3 is used as the baud rate generator is shown below B baud rate f BRG S3TM count clock frequency Hz D reload value 0 to 255 Even if the reload value is written to the SCI3 timer register the content of the SCI3 timer counter does not change If the SCI3 timer is used as the auto reload timer baud rate generator from the beginning of an operati...

Page 260: ...truction is executed the watchdog timer is overflown or an operation code trap is generated S4TM becomes 0000H and the count operation stops 3 SCI4 Timer Control Register S4CON S4CON is an 8 bit register The high order 4 bits bits 4 7 select the count clock of S4TM and controls the start stop of the count operation The low order 2 bits bits 2 and 3 perform interrupt related controls The least sign...

Page 261: ...r mode 1 S4TM baud rate generator mode for SCI4 0 SCI4 timer counter overflow generation no 1 SCI4 timer counter overflow generation yes 0 SCI4 timer counter count operation STOP 1 SCI4 timer counter count operation RUN S4CK Count Clock of S4TM 2 1 0 0 0 0 Master clock CLK 0 0 1 1 2 CLK 0 1 0 1 2 TBCCLK 0 1 1 1 4 TBCCLK 1 0 0 1 8 TBCCLK 1 0 1 1 16 TBCCLK 1 1 0 1 64 TBCCLK 1 1 1 1 256 TBCCLK indica...

Page 262: ...low is generated The calculation of the baud rate when SCI4 is used as the baud rate generator is shown below B baud rate f BRG S4TM count clock frequency Hz D reload value 0 to 255 Even if the reload value is written to the SCI4 timer register the content of the SCI4 timer counter does not change If the SCI4 timer is used as the auto reload timer baud rate generator from the beginning of an opera...

Page 263: ...14 18 MSM66591 ML66592User sManual Chapter 14 Baud Rate Generator Functions ...

Page 264: ...Serial Port Functions Chapter 15 15 ...

Page 265: ......

Page 266: ...ode and a 4 stage buffer mode Single buffer mode has a single stage of receive buffer and 4 stage buffer mode has four stages of receive buffers ring buffer type Synchronous mode has a master mode to generate the internal MSM66591 ML66592 shift clock and a slave mode to receive the shift clock supply that is external Table 15 1 lists the serial port modes Table 15 1 Serial Port Mode Serial Port No...

Page 267: ...gisters S0STATm S1STAT S2STATm S3STATm S4STATm m 0 2 a transmit register and a receive register Figure 15 1 shows the configuration of SCI0 SCI2 SCI3 and SCI4 Figure 15 2 shows the configuration of SCI1 Table 15 2 lists the serial port control SFRs TXDn n 0 P6_7 n 2 P9_1 n 3 P9_3 n 4 P9_5 RXDn n 0 P6_6 n 2 P9_0 n 3 P9_2 n 4 P9_4 SRnCON SnBUF0 SnSTAT0 STnCON SnBUF0 SnTM 8 Bit Timer Receive Register...

Page 268: ...r 1 S4BUF1 Undefined 0036 SCI4 Receive Buffer Register 2 S4BUF2 Undefined 0037 SCI4 Receive Buffer Register 3 S4BUF3 Undefined 0038 SCI0 Status Register 0 S0STAT0 00 0039 SCI0 Interrupt Control Register SR0INT 01 003A SCI2 Status Register 0 S3STAT0 00 003B SCI2 Interrupt Control Register SR3INT 01 003C SCI3 Status Register 0 S4STAT0 00 003D SCI3 Interrupt Control Register SR4INT 01 003E SCI4 Statu...

Page 269: ...AT1 11 0193 SCI2 Status Register 2 S3STAT2 C1 0194 SCI3 Status Register 1 S4STAT1 0195 SCI3 Status Register 2 S4STAT2 0196 SCI4 Status Register 1 0197 SCI4 Status Register 2 11 C1 11 C1 S0STAT1 S0STAT2 R W 8 8 16 Bit Operation Some addresses are not consecutive Addresses in the address column marked by indicate that the register has bits missing Address H Name Abbreviated Name BYTE Abbreviated Nam...

Page 270: ... not provided for the transmit side Figure 15 3 shows the configuration of ST0CON Description of Each Bit ST0MD bit 0 This bit specifies the transmit operation mode of SCI0 ST0MPC bit 2 If SCI0 transmits in UART multiprocessor communication mode this bit specifies which is transmitted data or an address The transmit data length is 8 bits If this bit is 0 data is transmitted and if 1 an address is ...

Page 271: ...D 7 6 5 4 3 2 1 0 indicates a bit that is not provided 1 is read if a read instruction is executed 0 SCI0 UART normal mode 1 SCI0 UART multiprocessor communication mode 0 Data transmitted 1 Address transmitted 0 2 stop bits 1 1 stop bit Multiprocessor communication mode Parity bit no Parity bit yes Odd parity Even parity 0 1 0 1 ST0CON ...

Page 272: ...ives in UART multiprocessor communication mode this bit specifies which is received data or an address The receive data length is 8 bits If this bit is 0 data is received and if 1 an address is received SR0EXP bit 3 This bit specifies the SCI0 receive buffer mode If this bit is 0 only S0BUF0 is enabled as a receive buffer single buffer mode and if 1 S0BUF0 S0BUF1 S0BUF2 and S0BUF3 are enabled as a...

Page 273: ...hat is not provided 1 is read if a read instruction is executed 0 SCI0 UART normal mode 1 SCI0 UART multiprocessor communication mode 0 Data is received 1 Address is received 0 1 0 1 0 1 Multiprocessor communication mode Parity bit no Parity bit yes Odd parity Even parity SCI0 receive disabled SCI0 receive enabled SR0CON 0 Single buffer mode 1 4 stage buffer mode receive side ...

Page 274: ...ge buffer mode These registers are read only and cannot be written to During the 4 stage buffer mode at the completion of each 1 byte reception the contents of the receive register are transferred to a receive buffer register in the order of S0BUF0 S0BUF1 S0BUF2 S0BUF3 S0BUF0 etc At the same time a receive interrupt request is generated Ring Buffer Type When the receive mode is the UART multiproce...

Page 275: ...its of S0STAT0 by the program when a receive ends The contents of S0BUF0 must be read before resetting OERR00 bit 1 of the low order 4 bits of S0STAT0 Otherwise the OERR00 flag is set to 1 again irrespective of occurrence of an overrun error in next receive operation During the 4 stage buffer mode an overrun error flag parity error flag and multi processor communication flag are provided for each ...

Page 276: ...CI0 UART multi processor communication mode This means that if the MPC bit of the data that is transferred when the SR0MPC bit of SR0CON is 0 is 1 MERR00 is set inter preting this as a multiprocessor communication error RV0IE0 bit 4 This bit enables disables the generation of an SCI0 receive ready interrupt request If this bit is 1 generation is enabled and if 0 generation is disabled RV0IRQ0 bit ...

Page 277: ...F0 parity error yes 0 S0BUF0 multiprocessor communication error no 1 S0BUF0 multiprocessor communication error yes 0 S0BUF0 receive ready interrupt request generation disabled 1 S0BUF0 receive ready interrupt request generation enabled 0 S0BUF0 receive ready generation no 1 S0BUF0 receive ready generation yes 0 SCI0 transmit ready interrupt request generation disabled 1 SCI0 transmit ready interru...

Page 278: ...eset when the RES signal is input the BRK instruction is executed the watchdog timer is overflown or an operation code trap is generated S0STAT1 becomes 11H Figure 15 6 shows the configuration of S0STAT1 Description of Each Bit OERR01 bit 1 When an SCI0 receive operation is complete and the receive data is transferred into S0BUF1 OERR01 is set to 1 if the data transferred into S0BUF1 for the previ...

Page 279: ...bit of SR0CON is 0 is 1 MERR02 is set to 1 interpreting this as a multiprocessor communication error Figure 15 6 Configuration of S0STAT1 7 MERR02 6 PERR02 5 OERR02 4 3 MERR01 2 PERR01 1 OERR01 0 0 1 S0BUF1 overrun error no S0BUF1 overrun error yes 0 1 0 1 S0BUF1 multiprocessor communication error no S0BUF1 multiprocessor communication error yes S0BUF1 parity error no S0BUF1 parity error yes 0 1 S...

Page 280: ...eive buffer into which data will be transferred S0BUF0 S0BUF1 S0BUF2 S0BUF3 can be verified by reading bits 4 and 5 of S0STAT2 At reset when the RES signal is input the BRK instruction is executed the watchdog timer is overflown or an operation code trap is generated S0STAT2 becomes C1H Figure 15 7 shows the configuration of S0STAT2 Description of Each Bit OERR03 bit 1 When an SCI0 receive operati...

Page 281: ...r yes 0 1 0 1 S0BUF3 multiprocessor communication error no S0BUF3 multiprocessor communication error yes S0BUF3 parity error no S0BUF3 parity error yes BFCU0 1 Buffer counter monitor during SCI0 4 stage buffer mode indicates a bit that is not provided 1 is read if a read instruction is executed 0 0 0 0 1 1 0 1 1 Write to S0BUF0 next Write to S0BUF1 next Write to S0BUF2 next Write to S0BUF3 next S0...

Page 282: ...nabled and if 0 generation is disabled RV0IE2 bit 2 This bit enables or disables the generation of SCI0 S0BUF2 receive ready interrupt requests If this bit is 1 generation is enabled and if 0 generation is disabled RV0IE3 bit 3 This bit enables or disables the generation of SCI0 S0BUF3 receive ready interrupt requests If this bit is 1 generation is enabled and if 0 generation is disabled RV0IRQ0 b...

Page 283: ...n enabled 0 1 S0BUF3 receive ready interrupt request generation disabled S0BUF3 receive ready interrupt request generation enabled 0 1 S0BUF0 receive ready generation no see note S0BUF0 receive ready generation yes see note 0 1 S0BUF1 receive ready generation no S0BUF1 receive ready generation yes 0 1 S0BUF2 receive ready generation no S0BUF2 receive ready generation yes 0 1 S0BUF3 receive ready g...

Page 284: ...T synchronous multiprocessor communication mode bit 2 ST1MPC specifies which is transmitted data or an address The transmit data length is fixed at 8 bits If bit 2 ST1MPC is 0 data is transmitted and if 1 an address is transmitted ST1STB ST1MST bit 4 The function of bit 4 differs depending on the operation mode specified by bit 1 and 0 When SCI1 transmits in UART mode bit 4 ST1STB specifies the st...

Page 285: ...T1MST indicates a bit that is not provided 1 is read if a read instruction is executed ST1MD SCI1 Transmit Operation Mode 1 0 0 0 UART normal mode 0 1 UART multiprocessor communication mode 1 0 Synchronous normal mode 1 1 Synchronous multiprocessor communication mode 0 Data transmit 1 Address transmit 0 2 stop bits 1 1 stop bit 0 Transmit in slave mode 1 Transmit in master mode 0 Parity bit no 1 P...

Page 286: ... If SCI1 receives in UART synchronous multiprocessor communication mode bit 2 SR1MPC specifies which is received data or an address The receive data is 8 bit data length If bit 2 SR1MPC is 0 data is received and if 1 an address is received SR1MST bit 4 The function of bit 4 differs depending on the operation mode specified by bits 1 and 0 When SCI1 receives in UART mode bit 4 is meaningless When S...

Page 287: ...ded 1 is read if a read instruction is executed SR1MD SCI1 Receive Operation Mode 1 0 0 0 UART normal mode 0 1 UART multi processor communication mode 1 0 Synchronous normal mode 1 1 Synchronous multiprocessor communication mode 0 Data receive 1 Address receive 0 Receive in slave mode 1 Receive in master mode 0 Parity bit no 1 Parity bit yes 0 Odd parity 1 Even parity 0 SCI1 receive disable 1 SCI1...

Page 288: ...ceive registers are two 8 bit shift registers that actually per form shift operations during a transmit receive operation The transmit and receive registers and transmit receive buffer register S1BUF have a double structure When a receive operation ends the data received by the receive register is transferred to S1BUF and a receive interrupt request is generated The transmit and receive registers ...

Page 289: ...processor communication mode This means that if the MPC bit of the data that is transferred when the SR1MPC bit of SR1CON is 0 is 1 MERR1 is set interpreting this as a multiprocessor communication error RV1IE bit 4 This bit enables disables the generation of an SCI1 receive ready interrupt request If this bit is 1 generation is enabled and if 0 generation is disabled RV1IRQ bit 5 This bit is set t...

Page 290: ...cessor communication error no 1 SCI1 multiprocessor communication error yes 0 SCI1 receive ready interrupt request generation disabled 1 SCI1 receive ready interrupt request generation enabled 0 SCI1 receive ready generation no 1 SCI1 receive ready generation yes 0 SCI1 transmit ready interrupt request generation disabled 1 SCI1 transmit ready interrupt request generation enabled 0 SCI1 transmit r...

Page 291: ...he transmit side Figure 15 12 shows the configuration of ST2CON Description of Each Bit ST2MD bit 0 This bit specifies the transmit operation mode of SCI2 ST2MPC bit 2 If SCI2 transmits in UART multiprocessor communication mode this bit specifies which is transmitted data or an address The transmit data length is 8 bits If this bit is 0 data is transmitted and if 1 an address is transmitted ST2STB...

Page 292: ...2MD 7 6 5 4 3 2 1 0 indicates a bit that is not provided 1 is read if a read instruction is executed 0 SCI2 UART normal mode 1 SCI2 UART multiprocessor communication mode 0 Data transmitted 1 Address transmitted 0 2 stop bits 1 1 stop bit Multiprocessor communication mode Parity bit no Parity bit yes Odd parity Even parity 0 1 0 1 ST2CON ...

Page 293: ...ves in UART multiprocessor communication mode this bit specifies which is received data or an address The receive data length is 8 bits If this bit is 0 data is received and if 1 an address is received SR2EXP bit 3 This bit specifies the SCI2 receive buffer mode If this bit is 0 only S2BUF0 is enabled as a receive buffer single buffer mode and if 1 S2BUF0 S2BUF1 S2BUF2 and S2BUF3 are enabled as a ...

Page 294: ...t that is not provided 1 is read if a read instruction is executed 0 SCI2 UART normal mode 1 SCI2 UART multiprocessor communication mode 0 Data is received 1 Address is received 0 1 0 1 0 1 Multiprocessor communication mode Parity bit no Parity bit yes Odd parity Even parity SCI2 receive disabled SCI2 receive enabled SR2CON 0 Single buffer mode 1 4 stage buffer mode receive side ...

Page 295: ... received data when the SR2EXP bit of SR2CON is set to 1 4 stage buffer mode These registers are read only and cannot be written to During the 4 stage buffer mode at the completion of each 1 byte reception the contents of the receive register are transferred to a receive buffer register in the order of S2BUF0 S2BUF1 S2BUF2 S2BUF3 S2BUF0 etc At the same time a receive interrupt request is generated...

Page 296: ...bits of S2STAT0 by the program when a receive ends The contents of S2BUF0 must be read before resetting OERR20 bit 1 of the low order 4 bits of S2STAT0 Otherwise the OERR20 flag is set to 1 again irrespective of occurrence of an overrun error in next receive operation During the 4 stage buffer mode an overrun error flag parity error flag and multi processor communication flag are provided for each...

Page 297: ...2 UART multi processor communication mode This means that if the MPC bit of the data that is transferred when the SR2MPC bit of SR2CON is 0 is 1 MERR20 is set inter preting this as a multiprocessor communication error RV2IE0 bit 4 This bit enables disables the generation of an SCI2 receive ready interrupt request If this bit is 1 generation is enabled and if 0 generation is disabled RV2IRQ0 bit 5 ...

Page 298: ...BUF0 parity error yes 0 S2BUF0 multiprocessor communication error no 1 S2BUF0 multiprocessor communication error yes 0 S2BUF0 receive ready interrupt request generation disabled 1 S2BUF0 receive ready interrupt request generation enabled 0 S2BUF0 receive ready generation no 1 S2BUF0 receive ready generation yes 0 SCI2 transmit ready interrupt request generation disabled 1 SCI2 transmit ready inter...

Page 299: ...et when the RES signal is input the BRK instruction is executed the watchdog timer is overflown or an operation code trap is generated S2STAT1 becomes 11H Figure 15 15 shows the configuration of S2STAT1 Description of Each Bit OERR21 bit 1 When an SCI2 receive operation is complete and the receive data is transferred into S2BUF1 OERR21 is set to 1 if the data transferred into S2BUF1 for the previo...

Page 300: ... bit of SR2CON is 0 is 1 MERR22 is set to 1 interpreting this as a multiprocessor communication error Figure 15 15 Configuration of S2STAT1 7 MERR22 6 PERR22 5 OERR22 4 3 MERR21 2 PERR21 1 OERR21 0 0 1 S2BUF1 overrun error no S2BUF1 overrun error yes 0 1 0 1 S2BUF1 multiprocessor communication error no S2BUF1 multiprocessor communication error yes S2BUF1 parity error no S2BUF1 parity error yes 0 1...

Page 301: ...ve buffer into which data will be transferred S2BUF0 S2BUF1 S2BUF2 S2BUF3 can be verified by reading bits 4 and 5 of S2STAT2 At reset when the RES signal is input the BRK instruction is executed the watchdog timer is overflown or an operation code trap is generated S2STAT2 becomes C1H Figure 15 16 shows the configuration of S2STAT2 Description of Each Bit OERR23 bit 1 When an SCI2 receive operatio...

Page 302: ...ror yes 0 1 0 1 S2BUF3 multiprocessor communication error no S2BUF3 multiprocessor communication error yes S2BUF3 parity error no S2BUF3 parity error yes BFCU2 1 Buffer counter monitor during SCI2 4 stage buffer mode 0 0 0 0 1 1 0 1 1 Write to S2BUF0 next Write to S2BUF1 next Write to S2BUF2 next Write to S2BUF3 next indicates a bit that is not provided 1 is read if a read instruction is executed ...

Page 303: ...abled and if 0 generation is disabled RV2IE2 bit 2 This bit enables or disables the generation of SCI2 S2BUF2 receive ready interrupt requests If this bit is 1 generation is enabled and if 0 generation is disabled RV2IE3 bit 3 This bit enables or disables the generation of SCI2 S2BUF3 receive ready interrupt requests If this bit is 1 generation is enabled and if 0 generation is disabled RV2IRQ0 bi...

Page 304: ...ion enabled 0 1 S2BUF3 receive ready interrupt request generation disabled S2BUF3 receive ready interrupt request generation enabled 0 1 S2BUF0 receive ready generation no see note S2BUF0 receive ready generation yes see note 0 1 S2BUF1 receive ready generation no S2BUF1 receive ready generation yes 0 1 S2BUF2 receive ready generation no S2BUF2 receive ready generation yes 0 1 S2BUF3 receive ready...

Page 305: ...he transmit side Figure 15 18 shows the configuration of ST3CON Description of Each Bit ST3MD bit 0 This bit specifies the transmit operation mode of SCI3 ST3MPC bit 2 If SCI3 transmits in UART multiprocessor communication mode this bit specifies which is transmitted data or an address The transmit data length is 8 bits If this bit is 0 data is transmitted and if 1 an address is transmitted ST3STB...

Page 306: ...3MD 7 6 5 4 3 2 1 0 indicates a bit that is not provided 1 is read if a read instruction is executed 0 SCI3 UART normal mode 1 SCI3 UART multiprocessor communication mode 0 Data transmitted 1 Address transmitted 0 2 stop bits 1 1 stop bit Multiprocessor communication mode Parity bit no Parity bit yes Odd parity Even parity 0 1 0 1 ST3CON ...

Page 307: ...3 receives in UART multiprocessor communication mode this bit specifies which is received data or an address The receive data length is 8 bits If this bit is 0 data is received and if 1 an address is received SR3EXP bit 3 This bit specifies the SCI3 receive buffer mode If this bit is 0 only S3BUF0 is enabled as a receive buffer single buffer mode and if 1 S3BUF0 S3BUF1 S3BUF2 and S3BUF3 are enable...

Page 308: ...t that is not provided 1 is read if a read instruction is executed 0 SCI3 UART normal mode 1 SCI3 UART multiprocessor communication mode 0 Data is received 1 Address is received 0 1 0 1 0 1 Multiprocessor communication mode Parity bit no Parity bit yes Odd parity Even parity SCI3 receive disabled SCI3 receive enabled SR3CON 0 Single buffer mode 1 4 stage buffer mode receive side ...

Page 309: ...d received data when the SR3EXP bit of SR3CON is set to 1 4 stage buffer mode These registers are read only and cannot be written to During the 4 stage buffer mode at the completion of each 1 byte reception the contents of the receive register is transferred to a receive buffer register in the order of S3BUF0 S3BUF1 S3BUF2 S3BUF3 S3BUF0 etc At the same time a receive interrupt request is generated...

Page 310: ...bits of S3STAT0 by the program when a receive ends The contents of S3BUF0 must be read before resetting OERR30 bit 1 of the low order 4 bits of S3STAT0 Otherwise the OERR30 flag is set to 1 again irrespective of occurrence of an overrun error in next receive operation During the 4 stage buffer mode an overrun error flag parity error flag and multi processor communication flag are provided for each...

Page 311: ...3 UART multi processor communication mode This means that if the MPC bit of the data that is transferred when the SR3MPC bit of SR3CON is 0 is 1 MERR30 is set inter preting this as a multiprocessor communication error RV3IE0 bit 4 This bit enables disables the generation of an SCI3 receive ready interrupt request If this bit is 1 generation is enabled and if 0 generation is disabled RV3IRQ0 bit 5 ...

Page 312: ...BUF0 parity error yes 0 S3BUF0 multiprocessor communication error no 1 S3BUF0 multiprocessor communication error yes 0 S3BUF0 receive ready interrupt request generation disabled 1 S3BUF0 receive ready interrupt request generation enabled 0 S3BUF0 receive ready generation no 1 S3BUF0 receive ready generation yes 0 SCI3 transmit ready interrupt request generation disabled 1 SCI3 transmit ready inter...

Page 313: ...et when the RES signal is input the BRK instruction is executed the watchdog timer is overflown or an operation code trap is generated S3STAT1 becomes 11H Figure 15 21 shows the configuration of S3STAT1 Description of Each Bit OERR31 bit 1 When an SCI3 receive operation is complete and the receive data is transferred into S3BUF1 OERR31 is set to 1 if the data transferred into S3BUF1 for the previo...

Page 314: ... bit of SR3CON is 0 is 1 MERR32 is set to 1 interpreting this as a multiprocessor communication error Figure 15 21 Configuration of S3STAT1 7 MERR32 6 PERR32 5 OERR32 4 3 MERR31 2 PERR31 1 OERR31 0 0 1 S3BUF1 overrun error no S3BUF1 overrun error yes 0 1 0 1 S3BUF1 multiprocessor communication error no S3BUF1 multiprocessor communication error yes S3BUF1 parity error no S3BUF1 parity error yes 0 1...

Page 315: ...ve buffer into which data will be transferred S3BUF0 S3BUF1 S3BUF2 S3BUF3 can be verified by reading bits 4 and 5 of S3STAT2 At reset when the RES signal is input the BRK instruction is executed the watchdog timer is overflown or an operation code trap is generated S3STAT2 becomes C1H Figure 15 22 shows the configuration of S3STAT2 Description of Each Bit OERR33 bit 1 When an SCI3 receive operatio...

Page 316: ...ror yes 0 1 0 1 S3BUF3 multiprocessor communication error no S3BUF3 multiprocessor communication error yes S3BUF3 parity error no S3BUF3 parity error yes BFCU3 1 Buffer counter monitor during SCI3 4 stage buffer mode 0 0 0 0 1 1 0 1 1 Write to S3BUF0 next Write to S3BUF1 next Write to S3BUF2 next Write to S3BUF3 next indicates a bit that is not provided 1 is read if a read instruction is executed ...

Page 317: ...abled and if 0 generation is disabled RV3IE2 bit 2 This bit enables or disables the generation of SCI3 S3BUF2 receive ready interrupt requests If this bit is 1 generation is enabled and if 0 generation is disabled RV3IE3 bit 3 This bit enables or disables the generation of SCI3 S3BUF3 receive ready interrupt requests If this bit is 1 generation is enabled and if 0 generation is disabled RV3IRQ0 bi...

Page 318: ...ion enabled 0 1 S3BUF3 receive ready interrupt request generation disabled S3BUF3 receive ready interrupt request generation enabled 0 1 S3BUF0 receive ready generation no see note S3BUF0 receive ready generation yes see note 0 1 S3BUF1 receive ready generation no S3BUF1 receive ready generation yes 0 1 S3BUF2 receive ready generation no S3BUF2 receive ready generation yes 0 1 S3BUF3 receive ready...

Page 319: ...he transmit side Figure 15 24 shows the configuration of ST4CON Description of Each Bit ST4MD bit 0 This bit specifies the transmit operation mode of SCI4 ST4MPC bit 2 If SCI4 transmits in UART multiprocessor communication mode this bit specifies which is transmitted data or an address The transmit data length is 8 bits If this bit is 0 data is transmitted and if 1 an address is transmitted ST4STB...

Page 320: ... 7 6 5 4 3 2 1 0 indicates a bit that is not provided 1 is read if a read instruction is executed 0 SCI4 UART normal mode 1 SCI4 UART multiprocessor communication mode 0 Data is transmitted 1 Address is transmitted 0 2 stop bits 1 1 stop bit Multiprocessor communication mode Parity bit no Parity bit yes Odd parity Even parity 0 1 0 1 ST4CON ...

Page 321: ...4 receives in UART multiprocessor communication mode this bit specifies which is received data or an address The receive data length is 8 bits If this bit is 0 data is received and if 1 an address is received SR4EXP bit 3 This bit specifies the SCI4 receive buffer mode If this bit is 0 only S4BUF0 is enabled as a receive buffer single buffer mode and if 1 S4BUF0 S4BUF1 S4BUF2 and S4BUF3 are enable...

Page 322: ...t that is not provided 1 is read if a read instruction is executed 0 SCI4 UART normal mode 1 SCI4 UART multiprocessor communication mode 0 Data is received 1 Address is received 0 1 0 1 0 1 Multiprocessor communication mode Parity bit no Parity bit yes Odd parity Even parity SCI4 receive disabled SCI4 receive enabled SR4CON 0 Single buffer mode 1 4 stage buffer mode receive side ...

Page 323: ...d received data when the SR4EXP bit of SR4CON is set to 1 4 stage buffer mode These registers are read only and cannot be written to During the 4 stage buffer mode at the completion of each 1 byte reception the contents of the receive register is transferred to a receive buffer register in the order of S4BUF0 S4BUF1 S4BUF2 S4BUF3 S4BUF0 etc At the same time a receive interrupt request is generated...

Page 324: ...bits of S4STAT0 by the program when a receive ends The contents of S4BUF0 must be read before resetting OERR40 bit 1 of the low order 4 bits of S4STAT0 Otherwise the OERR40 flag is set to 1 again irrespective of occurrence of an overrun error in next receive operation During the 4 stage buffer mode an overrun error flag parity error flag and multi processor communication flag are provided for each...

Page 325: ...4 UART multi processor communication mode This means that if the MPC bit of the data that is transferred when the SR4MPC bit of SR4CON is 0 is 1 MERR40 is set inter preting this as a multiprocessor communication error RV4IE0 bit 4 This bit enables disables the generation of an SCI4 receive ready interrupt request If this bit is 1 generation is enabled and if 0 generation is disabled RV4IRQ0 bit 5 ...

Page 326: ...BUF0 parity error yes 0 S4BUF0 multiprocessor communication error no 1 S4BUF0 multiprocessor communication error yes 0 S4BUF0 receive ready interrupt request generation disabled 1 S4BUF0 receive ready interrupt request generation enabled 0 S4BUF0 receive ready generation no 1 S4BUF0 receive ready generation yes 0 SCI4 transmit ready interrupt request generation disabled 1 SCI4 transmit ready inter...

Page 327: ...et when the RES signal is input the BRK instruction is executed the watchdog timer is overflown or an operation code trap is generated S4STAT1 becomes 11H Figure 15 27 shows the configuration of S4STAT1 Description of Each Bit OERR41 bit 1 When an SCI4 receive operation is complete and the receive data is transferred into S4BUF1 OERR41 is set to 1 if the data transferred into S4BUF1 for the previo...

Page 328: ...bit of SR4CON is 0 is 1 MERR42 is set to 1 interpreting this as a multiprocessor communication error Figure 15 27 Configuration of S4STAT1 7 MERR42 6 PERR42 5 OERR42 4 3 MERR41 2 PERR41 1 OERR41 0 0 1 S4BUF1 overrun error no S4BUF1 overrun error yes 0 1 0 1 S4BUF1 multi processor communication error no S4BUF1 multi processor communication error yes S4BUF1 parity error no S4BUF1 parity error yes 0 ...

Page 329: ...ve buffer into which data will be transferred S4BUF0 S4BUF1 S4BUF2 S4BUF3 can be verified by reading bits 4 and 5 of S4STAT2 At reset when the RES signal is input the BRK instruction is executed the watchdog timer is overflown or an operation code trap is generated S4STAT2 becomes C1H Figure 15 28 shows the configuration of S4STAT2 Description of Each Bit OERR43 bit 1 When an SCI4 receive operatio...

Page 330: ...ror yes 0 1 0 1 S4BUF3 multiprocessor communication error no S4BUF3 multiprocessor communication error yes S4BUF3 parity error no S4BUF3 parity error yes BFCU4 1 Buffer counter monitor during SCI4 4 stage buffer mode 0 0 0 0 1 1 0 1 1 Write to S4BUF0 next Write to S4BUF1 next Write to S4BUF2 next Write to S4BUF3 next indicates a bit that is not provided 1 is read if a read instruction is executed ...

Page 331: ...abled and if 0 generation is disabled RV4IE2 bit 2 This bit enables or disables the generation of SCI4 S4BUF2 receive ready interrupt requests If this bit is 1 generation is enabled and if 0 generation is disabled RV4IE3 bit 3 This bit enables or disables the generation of SCI4 S4BUF3 receive ready interrupt requests If this bit is 1 generation is enabled and if 0 generation is disabled RV4IRQ0 bi...

Page 332: ...ion enabled 0 1 S4BUF3 receive ready interrupt request generation disabled S4BUF3 receive ready interrupt request generation enabled 0 1 S4BUF0 receive ready generation no see note S4BUF0 receive ready generation yes see note 0 1 S4BUF1 receive ready generation no S4BUF1 receive ready generation yes 0 1 S4BUF2 receive ready generation no S4BUF2 receive ready generation yes 0 1 S4BUF3 receive ready...

Page 333: ...al M1S1 that indicates the beginning of an instruction execution and the interrupt request flag QSCIn is set to 1 When STnFREE becomes L level a start bit is generated synchronizing with the fall of the next STnCLK and the TXDn pin changes from H to L level at the rising edge of next CLK Hereafter transmit data LSB first and a parity bit are added according to the specifica tion of STnCON and a st...

Page 334: ...2 13 14 15 16 1 2 3 4 5 6 7 START BIT D LSB D MSB PARITY BIT STOP BIT STOP BIT NEXT START BIT Explanation of Symbols BRGn 1 16 BRGn STnCLK CLK WSnBUF LSTnSF STnFREE TXDn pin M1S1 TXnREADY n 0 4 clock pulse generated by baud rate generator SnTM BRGn divided by 16 transmit shift clock master clock write signal to SnBUF transmit start signal signal that indicates transmitting 0 transmit data output f...

Page 335: ...ion and the interrupt request flag QSCI1 is set to 1 When ST1FREE becomes L level the transmit shift clock is output from the TXC1 pin in synchronization with the falling edge of the second ST1CLK and at the rising edge of next CLK bit 0 LSB first of the transmit data is output from the TXD1 pin Hereafter transmit data and a parity bit are added synchronizing with TXC1 ST1CLK according to the spec...

Page 336: ...ded by 1 4 transmit shift clock transmit shift clock output from pin P6_5 master clock write signal to S1BUF transmit start signal signal that indicates transmitting 0 transmit data output from pin P6_3 signal that indicates beginning of an instruction transmit interrupt request signal Timing for ST1CLK generation by 1 4 BRG1 Transmit timing with parity bit D LSB D MSB PARITY BIT D LSB 1 2 3 4 BRG...

Page 337: ...ated synchronizing with the signal M1S1 that indicates the beginning of an instruction execution and the interrupt request flag QSCI1 is set to 1 When ST1FREE becomes L level at the rising edge of next CLK bit 0 LSB first is output from the TXD1 pin Bit 1 of the transmit data is output from the TXD1 pin at the rising edge of next CLK after the fall of ST1CLK Hereafter transmit data and a parity bi...

Page 338: ...pin TXD1 pin M1S1 TX1READY D LSB D bit 1 D MSB PARITY BIT D LSB Explanation of Symbols CLK TXC1 pin Edge detection ST1CLK WS1BUF LST1SF ST1FREE TXD1 pin M1S1 TX1READY master clock transmit shift clock input from pin P6_5 transmit shift clock in which TXC1 pin input edge is detected by CLK transmit shift clock write signal to S1BUF transmit start signal signal that indicates transmitting 0 transmit...

Page 339: ...t bit is judged as invalid and the receive operation is initialized SRnFREE becomes H level and then stops Receive data is sampled by 3 sampling clocks of the 1 16 division 7th 8th and 9th and 2 or more values of the sampled values are shifted in to the receive register as receive data by the 10th pulse SRnCLK Hereafter receive data continues to be received according to the specification of SRnCON...

Page 340: ...rt START BIT D LSB D MSB PARITY BIT STOP BIT STOP BIT NEXT START BIT D LSB 1 16 counter start 1 16 counter stop Explanation of Symbols BRGn Sampling CLKn CLK Edge detection LSRnBUF RXnREADY clock pulse generated by baud rate generator SnTM clock to sample receive data master clock receive data on which the RXDn signal edge is detected by CLK receive end signal receive interrupt request signal 1 16...

Page 341: ... from the RXC1 pin according to the specifica tion of SR1CON and receive data is sequentially shifted in the receive register If the final output of the receive shift clock ends the receive end signal LSR1BUF is generated synchronizing with the next SR1CLK If LSR1BUF is generated the content of the receive register receive data is trans ferred to S1BUF an overrun error and parity error if parity b...

Page 342: ...XC1 pin receive shift clock output from pin P6_4 INRXD receive data sampled from RXD1 by the RXD sampling clock signal that indicates beginning of an instruction M1S1 Sampling CLK1 WSR1CON SR1FREE signal that indicates receiving 0 write signal to SR1CON clock to sample data received at RXD1 Timing for generation of sampling CLK1 SR1CLK and RXC1 pin by 1 4 BRG BRG1 1 4 BRG1 Sampling CLK1 SR1CLK RXC...

Page 343: ...eive shift clock finally rises SR1CLK acquired by edge detection is generated and the final receive data is input Then 1 CLK later the receive end signal LSR1BUF is generated If LSR1BUF is generated the content of the receive register receive data is trans ferred to S1BUF an overrun error and parity error if parity bit exists are set the receive interrupt request signal RX1READY is generated synch...

Page 344: ...nation of Symbols CLK RXC1 pin Edge detection SR1CLK Sampling CLK1 master clock receive shift clock input from pin P6_4 receive shift clock in which RXC1 pin input edge is detected by CLK receive shift clock clock to sample receive data RXC1 L period Timing for generation of sampling CLK1 and SR1CLK by RXC1 pin edge detection ...

Page 345: ...ive shift clock write signal to SR1CON signal that indicates receiving 0 receive data input from pin P6_2 receive end signal receive interrupt request signal Explanation of Symbols Sampling CLK1 CLK SR1REN RXC1 pin INRXD M1S1 clock to sample receive data master clock receive enable signal bit 7 of SR1CON receive shift clock input from pin P6_4 receive data sampled from RXD1 by the RXD sampling clo...

Page 346: ...n process that data by an interrupt since the 3 bytes of data will be received in the order of S0BUF3 S0BUF0 and S0BUF1 enable interrupt generation only for S0BUF1 the last buffer to receive data and then begin the data reception To enable interrupt generation for S0BUF1 set RV0IE1 SCI0 receive interrupt enable flag of SR0INT to 1 In this case after reception is completed for S0BUF3 through S0BUF1...

Page 347: ...ion of Symbols Data 1 Data 2 Data 3 Data 4 Data 5 Data 1 Data 2 Data 3 Data 4 Data 5 1 frame 1 frame 1 frame 1 frame 1 frame LSRnBUF receive end signal RXnREADY receive interrupt request signal RxDn pin receive data input from pin M1S1 signal that indicates beginning of an instruction SnBUF0 SCIn receive buffer 0 SnBUF1 SCIn receive buffer 1 SnBUF2 SCIn receive buffer 2 SnBUF3 SCIn receive buffer ...

Page 348: ...A D Converter Functions Chapter 16 16 ...

Page 349: ......

Page 350: ...nerated A successive approximation method using the Sample Hold function is utilized to convert analog quantities to digital quantities The converted result is stored in the A D result registers ADCR0 ADCR23 Corresponding to ch0 ch23 pins AI0 AI23 are available as analog input only pins Operation of the A D converters is controlled by control registers located in the SFR area ADCON0L ADCON0H ADCON...

Page 351: ...Interrupt Request Selector Analog Selector Figure 16 1 Configuration of A D Converter 0 ADC0 For A D converter specifications see Chapter 25 Electrical Characteristics Figure 16 2 Configuration of A D Converter 1 ADC1 ADCR12 ADCR13 ADCR14 ADCR15 ADCR16 ADCR17 ADCR18 ADCR19 ADCR20 ADCR21 ADHENCON Internal Bus AVDD VREF AGND AI12 AI23 ADCON1L ADCR22 ADCR23 ADHSEL1 ADCON1H ADINTCON1 ADHSCON A D Conve...

Page 352: ... D Result Register 13 Undefined ADCR13 A D Result Register 14 Undefined ADCR14 A D Result Register 15 Undefined ADCR15 A D Result Register 16 Undefined ADCR16 A D Result Register 17 Undefined ADCR17 A D Result Register 18 Undefined ADCR18 A D Result Register 19 Undefined ADCR19 A D Result Register 20 Undefined ADCR20 A D Result Register 21 Undefined ADCR21 A D Result Register 22 Undefined ADCR22 A...

Page 353: ...for A D converter 1 is specified and A D conversion is performed for the specified channel The select mode is mainly controlled by the A D control register H ADCON0H ADCON1H It is also possible to operate select mode during scan mode operation In this case A D conversion for a channel that A D conversion is progressing for in scan mode is suspended at that point when select mode is specified and A...

Page 354: ...verflow 12 CAP15 event generation 13 FTM16 event generation 14 FTM17 event generation 15 Soft 0 bit 0 of ADHSCON set by the program 16 Soft 1 bit 1 of ADHSCON set by the program Interrupt Cause The A D hard select mode is controlled by the A D hard select register 0 ADHSEL0 A D hard select register 1 ADHSEL1 and A D hard select enable register ADHENCON An interrupt source to activate the A D hard ...

Page 355: ...mode interrupt source as the ongoing A D conversion is generated the ongoing A D conver sion is given priority and the generated A D conversion request is ignored Figure 16 4 shows the configuration of A D hard select mode Figure 16 4 A D Hard Select Mode Configuration Dxxx Exxx Qxxx Interrupt cause generation source Dxxx Exxx Qxxx Interrupt cause generation source Dxxx Exxx Qxxx Interrupt cause g...

Page 356: ...ecifies the A D conversion start factor in scan mode If this bit is 0 the next conversion starts when the A D conversion is over If this bit is 1 1 channel A D conversion starts at each valid edge of the external interrupt input pin INT1 At this time bit 1 of the Port 6 secondary function control register must be set to to 1 and the INT1 pin must be set to the secondary function Operation examples...

Page 357: ...rts at valid edge of INT1 0 Next conversion starts when cycle is completed 1 Conversion stops when cycle is completed 0 0 1 0 1 0 ch10 ch11 1 0 1 1 ch11 1 1 Setting inhibited ADCON0L SCNC0 bit 6 This bit specifies the operation after a scan channel cycle is completed If this bit is 0 A D conversion starts from the first channel again after a scan channel cycle is completed If this bit is 1 A D con...

Page 358: ...ersion start factor in scan mode If this bit is 0 the next conversion starts when the A D conversion is over If this bit is 1 1 channel A D conversion starts at each valid edge of the external interrupt input pin INT1 At this time bit 1 of the Port 6 secondary function control register must be set to to 1 and the INT1 pin must be set to the secondary function Operation examples 1 2 and 3 when SNEX...

Page 359: ... that setting ADRUN1 to 1 again by the program does not start A D conver sion again Figure 16 6 Configuration of ADCON1L SCNC1 SNEX1 ADRUN1 ADSNM13 ADSNM12 ADSNM11 ADSNM10 7 6 5 4 3 2 1 0 indicates a bit that is not provided 1 is read if a read instruction is executed ADSNM1 A D Converter 1 Scan Channel 3 2 1 0 0 0 0 0 ch12 ch23 0 0 0 1 ch13 ch23 0 0 1 0 ch14 ch23 0 0 1 1 ch15 ch23 0 1 0 0 ch16 ch...

Page 360: ...ct mode Change the select channel after setting STS0 bit 4 to 0 When STS0 is 1 when A D conversion is running in select mode changing the select channel is invalid STS0 bit 4 This bit specifies RUN STOP of A D conversion in select mode If this bit is 1 A D conversion of the channel specified by ADSTM00 ADSTM03 bit 0 bit 3 starts This bit becomes 0 when A D conversion ends ADTM00 ADTM01 bit 5 bit 6...

Page 361: ...is read if a read instruction is executed ADSTM0 A D Converter 0 Select Channel 3 2 1 0 0 0 0 0 ch0 0 0 0 1 ch1 0 0 1 0 ch2 0 0 1 1 ch3 0 1 0 0 ch4 0 1 0 1 ch5 0 1 1 0 ch6 0 1 1 1 ch7 1 0 0 0 ch8 1 1 ch9 0 Select mode A D conversion STOP 1 Select mode A D conversion RUN ADTM0 1 0 0 0 512 CLK 21 3 ms 0 1 384 CLK 1 256 CLK 1 0 1 0 ch10 1 0 1 1 ch11 1 1 Setting inhibited 0 0 Number of clocks for A D ...

Page 362: ...ct mode Change the select channel after setting STS1 bit 4 to 0 When STS1 is 1 when A D conversion is running in select mode changing the select channel is invalid STS1 bit 4 This bit specifies RUN STOP of A D conversion in select mode If this bit is 1 A D conversion of the channel specified by ADSTM10 ADSTM13 bit 0 bit 3 starts This bit becomes 0 when A D conversion ends ADTM10 ADTM11 bit 5 bit 6...

Page 363: ...ad if a read instruction is executed ADSTM1 A D Converter 1 Select Channel 3 2 1 0 0 0 0 0 ch12 0 0 0 1 ch13 0 0 1 0 ch14 0 0 1 1 ch15 0 1 0 0 ch16 0 1 0 1 ch17 0 1 1 0 ch18 0 1 1 1 ch19 1 0 0 0 ch20 1 1 ch21 0 Select mode A D conversion STOP 1 Select mode A D conversion RUN ADTM1 1 0 0 0 512 CLK 21 3 ms 0 1 384 CLK 1 256 CLK 1 0 1 0 ch22 1 0 1 1 ch23 1 1 Setting inhibited 0 0 Number of clocks for...

Page 364: ...sion in select mode If this bit is 1 A D conversion has ended This bit must be reset to 0 by the program ADSNIE0 bit 2 This bit specifies enable disable of an interrupt request generation when a scan channel cycle is completed If this bit is 0 the interrupt request generation is disabled and if 1 is enabled The phrase cycle is completed indicates that the A D conversion of ch11 is com pleted ADSTI...

Page 365: ...de end yes 0 Interrupt request generation by INTSN0 disabled 1 Interrupt request generation by INTSN0 enabled 0 Interrupt request generation by INTST0 disabled 1 Interrupt request generation by INTST0 enabled indicates a bit that is not provided 1 is read if a read instruction is executed 0 Hard Select mode end no 1 Hard Select mode end yes 0 Interrupt request generation by INTHS0 disabled 1 Inter...

Page 366: ...rsion in select mode If this bit is 1 A D conversion has ended This bit must be reset to 0 by the program ADSNIE1 bit 2 This bit specifies enable disable of an interrupt request generation when a scan channel cycle is completed If this bit is 0 the interrupt request generation is disabled and if 1 is enabled The phrase cycle is completed indicates that the A D conversion of ch23 is com pleted ADST...

Page 367: ...ode end yes 0 Interrupt request generation by INTSN1 disabled 1 Interrupt request generation by INTSN1 enabled 0 Interrupt request generation by INTST1 disabled 1 Interrupt request generation by INTST1 enabled indicates a bit that is not provided 1 is read if a read instruction is executed 0 Hard Select mode end no 1 Hard Select mode end yes 0 Interrupt request generation by INTHS1 disabled 1 Inte...

Page 368: ... cannot be executed At reset when the RES signal is input the BRK instruction is executed the watchdog timer is overflown or an operation code trap is generated ADHSEL0 becomes 0000H Description of Each Bit ADHSEL0 bit 0 bit 3 These four bits are used to set an A D hard select mode activation interrupt cause to channel 0 ADHSEL0 bit 4 bit 7 These four bits are used to set an A D hard select mode a...

Page 369: ...tion GTMC GEVC overflow CAP15 event generation FTM16 event generation FTM17 event generation Software 0 ADHSCON bit 0 set Software 1 ADHSCON bit 1 set 0 1 0 1 0 1 0 1 7 6 5 A D Hard Select Mode Activation Interrupt Cause to Channel 1 0 0 0 0 0 0 0 0 1 0 0 1 0 1 0 0 1 0 0 1 1 0 1 1 PWC0 PWC1 underflow or match PWC2 PWC3 underflow or match PWC4 PWC5 underflow or match PWC6 PWC7 underflow or match PW...

Page 370: ...ion GTMC GEVC overflow CAP15 event generation FTM16 event generation FTM17 event generation Software 0 ADHSCON bit 0 set Software 1 ADHSCON bit 1 set 0 1 0 1 0 1 0 1 15 14 13 A D Hard Select Mode Activation Interrupt Cause to Channel 3 0 0 0 0 0 0 0 0 1 0 0 1 0 1 0 0 1 0 0 1 1 0 1 1 PWC0 PWC1 underflow or match PWC2 PWC3 underflow or match PWC4 PWC5 underflow or match PWC6 PWC7 underflow or match ...

Page 371: ...cannot be executed At reset when the RES signal is input the BRK instruction is executed the watchdog timer is overflown or an operation code trap is generated ADHSEL1 becomes 0000H Description of Each Bit ADHSEL1 bit 0 bit 3 These four bits are used to set an A D hard select mode activation interrupt cause to channel 12 ADHSEL1 bit 4 bit 7 These four bits are used to set an A D hard select mode a...

Page 372: ...n GTMC GEVC overflow CAP15 event generation FTM16 event generation FTM17 event generation Software 0 ADHSCON bit 0 set Software 1 ADHSCON bit 1 set 0 1 0 1 0 1 0 1 7 6 5 A D Hard Select Mode Activation Interrupt Cause to Channel 13 0 0 0 0 0 0 0 0 1 0 0 1 0 1 0 0 1 0 0 1 1 0 1 1 PWC0 PWC1 underflow or match PWC2 PWC3 underflow or match PWC4 PWC5 underflow or match PWC6 PWC7 underflow or match PWC0...

Page 373: ...n GTMC GEVC overflow CAP15 event generation FTM16 event generation FTM17 event generation Software 0 ADHSCON bit 0 set Software 1 ADHSCON bit 1 set 0 1 0 1 0 1 0 1 15 14 13 A D Hard Select Mode Activation Interrupt Cause to Channel 15 0 0 0 0 0 0 0 0 1 0 0 1 0 1 0 0 1 0 0 1 1 0 1 1 PWC0 PWC1 underflow or match PWC2 PWC3 underflow or match PWC4 PWC5 underflow or match PWC6 PWC7 underflow or match P...

Page 374: ...elect mode the next A D conversion is reserved and will start after the present A D conversion is completed If 1 is written to bit 1 and bit 0 simultaneously A D conversion in the hard select mode due to bit 1 software 1 and A D conversion in the hard select mode due to bit 0 software 0 will be performed consecutively At reset when the RES signal is input the BRK instruction is executed the watchd...

Page 375: ...led and if 0 disabled ADHENC2 bit 2 This bit enables or disables hard select A D conversion on channel 2 If this bit is 1 the hard select of channel 2 is enabled and if 0 disabled ADHENC3 bit 3 This bit enables or disables hard select A D conversion on channel 3 If this bit is 1 the hard select of channel 3 is enabled and if 0 disabled ADHENC12 bit 4 This bit enables or disables hard select A D co...

Page 376: ...0 0 1 ch1 hard select mode disabled ch1 hard select mode enabled 0 1 ch2 hard select mode disabled ch2 hard select mode enabled 0 1 ch3 hard select mode disabled ch3 hard select mode enabled 0 1 ch12 hard select mode disabled ch12 hard select mode enabled 0 1 ch13 hard select mode disabled ch13 hard select mode enabled 0 1 ch14 hard select mode disabled ch14 hard select mode enabled 0 1 ch15 hard ...

Page 377: ... 8 bits of data are all read as 1s At reset when the RES signal is input the BRK instruction is executed the watchdog timer is overflown or an operation code trap is generated ADCR0 ADCR23 are undefined ADCRn registers are divided into even and odd numbered ADCR registers Data can be written to multiple registers in the same group at one time When data is written to ADCR0 the data is simultaneousl...

Page 378: ... the case when the A D hard select mode is activated with the same trigger for ch0 and ch1 When A D hard select modes of different priority levels ch0 ch1 are activated by the same edge A D conversion of the higher priority ch0 begins 1 clock after the M1S1 signal and A D conversion of the lower priority ch1 begins 1 clock after completion of the ch0 conversion Shaded areas of the figure below ind...

Page 379: ...e is re sumed Master clock CLK Select mode Scan mode Suspend Select mode Scan mode Resume Scan mode Select mode Interrupt request generation valid edge Hard select mode Hard select mode Completion 1 clock 1 clock 1 clock 1 clock First M1S1 after generation of valid edge Suspend Resume Completion 2 Activation of Hard Select Mode A D Conversion during Select Mode Operation When the valid edge for th...

Page 380: ... Interrupt request generation valid edge ch1 Completion Completion b ch0 high priority request is generated after ch1 low priority activation When a high priority hard select mode activation request is generated during A D conversion in a low priority hard select mode the low priority hard select mode is suspended and 1 clock after the first M1S1 signal following generation of the activation reque...

Page 381: ...16 32 MSM66591 ML66592User sManual Chapter 16 A D Converter Functions ...

Page 382: ...Transition Detector Functions Chapter 17 17 ...

Page 383: ......

Page 384: ...e configuration of TRNSCON high order bits 17 Transition Detector Functions The MSM66591 ML66592 have eight transition detector functions which detect the valid edges rise fall both edges of an input pin If the valid edge specified by TRNSCON is input to TRNS0 TRNS7 pins the corre sponding bit 0 to bit 7 of the transition detector TRNSIT is set to 1 Reset the bit of TRNSIT to 0 by the program TRNS...

Page 385: ...0 Rising edge 1 1 Both edges Valid edge of TRNS2 5 4 0 Falling edge 1 0 Rising edge 1 1 Both edges Valid edge of TRNS3 7 6 0 Falling edge 1 0 Rising edge 1 1 Both edges 7 TRNSCON bits 0 7 13 12 11 10 9 8 indicates either 0 or 1 Valid edge of TRNS4 1 0 0 Falling edge 1 0 Rising edge 1 1 Both edges Valid edge of TRNS5 3 2 0 Falling edge 1 0 Rising edge 1 1 Both edges Valid edge of TRNS6 5 4 0 Fallin...

Page 386: ... the correspond ing bit of TRNSIT to 0 Figure 17 3 shows the configuration of TRNSIT TRNSF7 TRNSF6 TRNSF5 TRNSF4 TRNSF3 TRNSF2 TRNSF1 TRNSF0 7 6 5 4 3 2 1 0 0 Valid edge not input to TRNS0 pin 1 Valid edge input to TRNS0 pin 0 Valid edge not input to TRNS1 pin 1 Valid edge input to TRNS1 pin 0 Valid edge not input to TRNS2 pin 1 Valid edge input to TRNS2 pin 0 Valid edge not input to TRNS3 pin 1 V...

Page 387: ...17 4 MSM66591 ML66592User sManual Chapter 17 Transition Detector Functions ...

Page 388: ...Peripheral Functions Chapter 18 18 ...

Page 389: ......

Page 390: ...the master clock The master clock CLK is the frequency generated by multiplying the original oscillation clock by 2 2 3 CLK is only available in the MSM66591 If the CLKOUT pin is used bit 6 of the Port 5 secondary function control register must be set to 1 18 2 RES Pin Valid Level Detection Function The RES pin valid level detection function is a flag that is set to 1 when the RES pin becomes L le...

Page 391: ...3 2 1 0 CKOUT CLKOUT Pin Output Clock 2 0 1 2 CLK 0 1 4 CLK 0 1 8 CLK 0 1 16 CLK 0 RES pin did not become L level 1 RES pin became L level 0 OE pin L level 1 OE pin H level 1 2 3 CLK MSM66591 only 1 1 3 CLK 1 0 0 1 1 0 1 0 0 1 0 1 indicates a bit that is not provided 1 is read if a read instruction is executed indicates either 0 or 1 PRPHF ...

Page 392: ...External Interrupt Request Function Chapter 19 19 ...

Page 393: ......

Page 394: ...ster to 1 A dedicated pin pin 1 is provided for NMI The valid edge of INT0 INT1 and INT2 can be specified using the external interrupt control register EXICON The valid edge of NMI can be specified using the NMI control register NMICON At reset when the RES signal is input the BRK instruction is executed the watchdog timer is overflown or an operation code trap is generated EXICON becomes C0H and ...

Page 395: ... a read instruction is executed EXICON EX2M Valid Edge of INT2 1 0 0 0 L level 0 1 Falling edge 1 0 Rising edge 1 1 Both edges Figure 19 1 Configuration of EXICON Figure 19 2 Configuration of NMICON NMIRD MIPF NMIM1 NMIM0 7 6 5 4 3 2 1 0 NMIM Valid Edge of NMI 1 0 0 Falling edge 1 0 Rising edge 1 1 Both edges 0 NMI pin L level 1 NMI pin H level indicates a bit that is not provided 1 is read if a r...

Page 396: ...Interrupt Request Processing Function Chapter 20 20 ...

Page 397: ......

Page 398: ...l Register 11 3C or BC C0 C0 00 00 00 00 00 00 00 00 C0 00 00 00 00 C0 00 00 00 00 Interrupt Request Register 1 Interrupt Enable Register 1 Interrupt Priority Control Register 00 NMI Control Register External Interrupt Control Register IRQ0L IRQ0H IRQ1L IRQ1H IRQ2L IE0L IE0H IE1L IE1H IP00L IP00H IP01L IP01H IP10L IP10H IP11L IP11H NMICON EXICON 8 8 16 8 Interrupt Enable Register 2 IE2L 8 8 16 Int...

Page 399: ...cesses which include Saving program counter PC Saving accumulator ACC Saving local register base LRB Saving program status word PSW Resetting the NMI request flag Disabling maskable interrupt acceptance Disabling multiple interrupt by the NMI itself Loading value written to vector tables 0008H 0009H to the program counter then executing the first instruction of the NMI process Fourteen cycle are r...

Page 400: ...ution 07F5H 07F6H 07F7H 07F8H 07F9H 07FAH 07FBH 07FFH 07F7H 07F8H 07F9H 07FAH 07FBH 07FCH 07FDH 07FFH PSWH LRBL LRBH ACCL ACCH CSR Undefined PCH 07F7H 07F8H 07F9H 07FAH 07FBH 07FCH 07FDH 07FFH PSWH LRBL LRBH ACCL ACCH CSR Undefined PCH SSP SSP SSP Before saving After RTI execution 07FCH 07FDH 07FEH 07FEH PCL 07FEH PCL 07F6H PSWL 07F6H PSWL 07F5H 07F5H At INT Program memory space is 128K bytes Figu...

Page 401: ...rrupts t Flag MIPF that enables disables all priorities y Register IPX0 IPX1 that sets the priority level Figure 20 2 shows a conceptual diagram of maskable interrupt control Table 20 2 lists the vector addresses and bit symbols for maskable interrupts Figure 20 2 Conceptual Diagram of Maskable Interrupt Control Dxxx Exxx MIE MIPF PX0xxx PX1xxx Qxxx Interrupt cause generation source LV3 LV2 LV1 LV...

Page 402: ...QPW23 QSCI0 QINT1 IRQ P0INT0 P0TM0OV P0TM1OV P0CAP0 P0CAP1 P0CAP2 P0CAP3 P0RTO4 P0RTO5 P0RTO6 P0RTO7 P0RTO8 P0RTO9 P0RTO10 P0RTO11 P0SCI1 P0STMOV P0GTMOV P0AD1 P0AD0 P0PW01 P0PW23 P0SCI0 P0INT1 IPX0 IE EINT0 ETM0OV ETM1OV ECAP0 ECAP1 ECAP2 ECAP3 ERTO4 ERTO5 ERTO6 ERTO7 ERTO8 ERTO9 ERTO10 ERTO11 ESCI1 ESTMOV EGTMOV EAD1 EAD0 EPW01 EPW23 ESC10 EINT1 P1INT0 P1TM0OV P1TM1OV P1CAP0 P1CAP1 P1CAP2 P1CAP3...

Page 403: ...interrupt is accepted A bit of IRQ can be set to 1 or 0 by the program At reset when the RES signal is input the BRK instruction is executed the watchdog timer is overflown or an operation code trap is generated IRQ0L IRQ0H IRQ1L and IRQ1H become 00H and IRQ2L becomes C0H 3 Interrupt Enable Register IE IE0L IE0H IE1L IE1H IE2L The IE is a register that specifies an interrupt generation enable disa...

Page 404: ...rflown or an operation code trap is generated IP00L IP00H IP10L IP10H IP01L IP01H IP11L and IP11H become 00H and IP20L and IP21L become C0H 6 Interrupt Priority Control Register IPX0 IP00L IP00H IP10L IP10H IP20L IPX1 IP01L IP01H IP11L IP11H IP21L As a pair IPX0 and IPX1 specify the priority of maskable interrupts If the corresponding bit of IPX0 and IPX1 for a maskable interrupt is PX0xxx and PX1...

Page 405: ... generation request is sent to the judgment logic of an interrupt priority and if the priority of the interrupt to be requested is higher than the highest priority of the interrupt in execution the interrupt is immediately generated If one or more interrupts are in execution when an interrupt generation request is sent to the judgment logic of an interrupt priority and if the priority of the inter...

Page 406: ...LROM of MEMSCON to 1 17 cycles are required be cause cycles required to save the code segment register CSR are added When an interrupt generation condition is fulfilled by setting IRQ IE IP or MIPF to 1 by an instruction the actual generation of the interrupt occurs after the execution of the next instruction after the instruction that set the IRQ IE IP or MIPF to 1 It is necessary to execute an R...

Page 407: ...20 10 MSM66591 ML66592User sManual Chapter 20 Interrupt Request Processing Function ...

Page 408: ...Bus Port Functions Chapter 21 21 ...

Page 409: ......

Page 410: ...r vice versa if the EA pin is at L level 21 1 1 Operation of P0 P1 P12_0 and P12_1 During a Program Memory Access When the internal program memory is accessed EA pin is at H level P0 P1 P12_0 and P12_1 operate as an I O port When the external program memory is accessed EA pin is at L level P0 operates as a port that outputs lower addresses and that inputs instruction P1 P12_0 and P12_1 ML66592 onl...

Page 411: ... P0_0 P0_7 P7_2 ALE A8 A16 P1_0 P1_7 P12_0 P7_3 PSEN O0 O7 A0 A7 A8 A16 OE CE MSM66591 External ROM 128K bytes MAX Latch Circuit Note Since in the ML66592 address 17 A17 is output from the P12_1 pin connect the P12_1 pin to A17 of the external ROM Up to 256K bytes can be accessed Figure 21 1 External ROM Connection Example MSM66591 21 2 2 External Program Memory Access Timing Figures 21 2 and 21 3...

Page 412: ...17 is the same as A8 A16 Figure 21 2 External Program Memory Access Timing No Wait Cycles P7_2 ALE CLK P7_3 PSEN AD0 AD7 P0_0 P0_7 A8 A16 P1_0 P1_7 P12_0 PC8 16 PC0 7 PC8 16 INST0 7 PC0 7 Number of wait cycles inserted according to the ROMRDY setting In this example 2 wait cycles Note 3 1 2 wait cycles are automatically inserted into the CPU in this case as well In the ML66592 the timing for A17 a...

Page 413: ...21 4 MSM66591 ML66592User sManual Chapter 21 Bus Port Functions ...

Page 414: ...Expansion Port Chapter 22 22 ...

Page 415: ......

Page 416: ...TB The data length is selectable as 8 bits or 16 bits Connection of devices such as a 74HC165 is assumed for external input and a 74HC595 is assumed for external output of the expansion port Because expansion port functions are assigned as secondary functions of Port 10 corresponding bits of the Port 10 secondary function control register must be set to 1 to use expansion port functions 22 1 Expan...

Page 417: ...ription of Each Bit EXPBUSY bit 0 This BUSY flag indicates that a data transfer is in progress This bit is read only and writes are ignored DATMOD bit 1 This bit specifies the bit length of the data transfer If 0 8 bits of data are transferred If 1 16 bits of data are transferred IOMOD bit 2 This bit specifies the data transfer direction If 0 data is input If 1 data is output Figure 22 2 EXTPCON C...

Page 418: ...is assumed that a 74HC165 or other shift register is connected externally Reading EXPTD causes the transfer input to start and the EXPBUSY flag to change to 1 When EXPTD is read the latch strobe SFTSTB changes to a L level Next when the shift clock SFTCLK rises external data SFTDAT is input When SFTCLK falls external data is latched internally and at the same time SFTSTB changes to a H level Exter...

Page 419: ...ft data is output in sync with the fall of the shift clock SFTCLK It is assumed that data is captured externally in sync with the rise of SFTCLK When SFTCLK outputs 8 clocks the transfer output is completed At the same time SFTSTB changes to a L level 1 shift clock later SFTSTB changes to a H level and data is latched externally During this 1 shift clock interval the shift clock is not output And ...

Page 420: ...Serial Port with FIFO SCI5 Chapter 23 23 ...

Page 421: ......

Page 422: ...elect pin P5_4 CS a read and write control pin P5_3 RWB a WAIT pin P5_7 WAIT with BUSY signal input and an interrupt input pin P5_5 INT2 are provided for use with the CAN controller If SCI5 is to be used set the following pins to their secondary function P5_0 SDIN P5_1 SDOUT P5_2 SCLK P5_3 RWB P5_4 CS P5_5 INT2 and P5_7 WAIT 23 1 SCI5 Configuration SCI5 consists of a data buffer FIFO an 8 bit SFDO...

Page 423: ...tialization this flag is automatically cleared This flag is used to initialize the FIFO pointer when commu nication is cut off S5EXIE bit 5 This flag enables or disables the generation of interrupt requests by the valid edge of external interrupt 2 INT2 If this bit is set to 1 the generation of interrupt requests is enabled If set to 0 the generation of interrupt requests is disabled S5RIE bit 6 T...

Page 424: ... 0 0 1 0 1 1 1 0 1 0 1 0 1 0 1 0 1 Interrupt request due to SCI5 receive completion disabled Interrupt request due to SCI5 receive completion enabled Interrupt request due to SCI5 transmit completion disabled Interrupt request due to SCI5 transmit completion enabled 1 1 Normal FIFO operation FIFO pointer initialization Interrupt request due to INT2 valid edge input disabled Interrupt request due t...

Page 425: ...it is automatically cleared If this bit is cleared during a reception the reception is immediately suspended and SCI5 is initialized TENT bit 5 This flag starts transmission Setting this bit to 1 will start transmission When the number of data bytes written to the SFDOUT transmit buffer are transmit ted this bit is automatically cleared If this bit is cleared during a transmission the transmission...

Page 426: ... individual interrupt request flag becomes 1 Because this flag is not automatically cleared even when an interrupt is processed it must be cleared by the program S5TIRQ bit 7 When SCI5 transmission is complete this individual interrupt request flag becomes 1 Because this flag is not automatically cleared even when an interrupt is processed it must be cleared by the program Figure 23 4 SCI5INT Conf...

Page 427: ... When the CAN controller is to be accessed for both transmission and reception the address written to SFADR is output from the SDOUT pin and then the data transmis sion or reception is performed At reset when the RES signal is input the BRK instruction is executed the watchdog timer is overflown or an operation code trap is generated SFADR becomes 00H Figure 23 5 shows the configuration of SFADR F...

Page 428: ...is overflown or an operation code trap is generated SFDIN becomes undefined Figure 23 6 shows the configuration of SFDIN Figure 23 7 SFDOUT Configuration Figure 23 6 SFDIN Configuration 23 7 Serial Data Output Register SFDOUT The serial data output register SFDOUT is an 8 bit register used to write transmit data 8 bytes max to the CAN controller This register is write only Do not attempt to read t...

Page 429: ... addresses beginning with the leading address that was transmitted first If the TENT bit is reset to 0 during a transfer the transmission is immediately sus pended and SCI5 initialized In this case the transmission contents are not saved When reading data from the CAN controller write the leading receive address 1 byte to the SCI5 s SFADR and then write the number of receive data bytes 1 8 bytes t...

Page 430: ...6 A7 A0 A1 A2 A3 A4 A5 A6 A7 D0 D1 D2 D3 D4 D5 D6 D7 D0 D0 D1 D2 D3 D4 D5 D6 D7 D1 D2 D3 SDIN R W CS SCLK SDOUT SDIN R W Address transmission Address reception BUSY reception WAIT input BUSY output Data R W Address update Data transmission and reception Data transmission and reception D0 D1 D2 D3 D4 D5 D6 D7 D0 D1 D2 D3 D0 D1 D2 D3 D4 D5 D6 D7 a Transmission b Reception M66591 CAN Cont Data transm...

Page 431: ...23 10 MSM66591 ML66592User sManual Chapter 23 Serial Port with FIFO SCI5 ...

Page 432: ...RAM Monitor Function Chapter 24 24 ...

Page 433: ......

Page 434: ... the RAM monitor function In the MSM66Q591 ML66Q592 flash EEPROM version the RAM monitor function cannot be used in the user mode used for reprogramming the flash EEPROM 24 1 Configuration of RAM Monitor Function Figure 24 1 shows the configuration of the RAM monitor function The RAM monitor function consists of a 21 bit shift register a ROM address buffer a RAM address buffer a RAM data register ...

Page 435: ...or Configuration RAM Address Pointer Program Counter Comparator Comparator RAM Address Buffer ROM Address Buffer RAM Data Register 21 bit Shift Register DIN P11_0 RMRX TEST for MSM66591 ML66592 EA for MSM66Q591 ML66Q592 P11_2 RMCLK CLK Control Circuit P11_3 RMACK P11_1 RMTX DOUT Data Bus ...

Page 436: ... or ROM address reception RAM address field bit 0 to bit 15 when setting a RAM address Sets the RAM address desired to be read ROM address field bit 0 to bit 17 when setting a ROM address Sets the ROM address that determines read timing for the RAM address desired to be read MODE bit 18 If setting a ROM address set the MODE bit to 1 If setting a RAM address set to 0 ENABLE bit 19 The enable bit sp...

Page 437: ...CLK RMRX bit 2 bit 1 bit 13 bit 14 bit 15 bit 16 bit 17 0 0 0 1 ENABLE GO bit 0 ROM address 18 bits MODE bit RMCLK RMTX bit 2 bit 1 bit 13 bit 14 bit 15 0 0 0 0 0 bit 0 RAM data 16 bits Dummy bits 1 RAM address setting 2 ROM address setting 3 RAM data read Note The operation of 1 and 3 are simultaneously performed in synchronization with RMCLK The operation of 2 and 3 are performed in the same man...

Page 438: ...M data desired to be read Set a ROM address in accordance with the ROM address setting timing diagram of Figure 24 2 2 Set MODE bit 1 ENABLE bit 1 and GO bit 1 When the RAM monitor function detects that the GO bit of the received ROM address is 1 the ROM address is loaded in the ROM address buffer and address comparison is started 2 Detection of address matching When data is written to the set RAM...

Page 439: ...e RAM monitor function is disabled and the control circuit is initialized In the MSM66591 ML66592 when the TEST pin is brought back to a L level the RAM monitor function is disabled and the control circuit is initialized When enabling the RAM monitor function externally apply a H level to the P11_0 RMRX pin and to the P11_2 RMCLK pin in advance ...

Page 440: ...ta register 0000H 5555H AAAAH Explanation of Symbols PCCMP RAMCMP A rise in this signal indicates that the set ROM address has matched the program counter A rise in this signal indicates that the set RAM address has matched the RAM address pointer Ignored H level H level H level Explanation of Symbols For the MSM66591 ML66592 mask ROM version it is the TEST pin that is used to set the RAM monitor ...

Page 441: ...24 8 MSM66591 ML66592User sManual Chapter 24 RAM Monitor Function ...

Page 442: ...25 Electrical Characteristics Chapter 25 ...

Page 443: ......

Page 444: ...eference voltage Analog input voltage VREF VHV 0 3 to VDD 0 3 and 0 3 to AVDD 0 3 0 3 to 13 25 Electrical Characteristics MSM66591 Electrical Characteristics 25 1 Absolute Maximum Ratings MSM66591 1 If this device is used in circumstances where the ambient temperature Ta exceeds 85 C be sure to contact your local Oki sales office in advance 2 Applied to TEST EA Only for MSM66Q591 Apply a high volt...

Page 445: ...rature Fanout MHz fOSC 0 Hz 1 VDD AVDD 20 MHz fOSC 24 MHz 1 Flash ROM programming cycle 3 Ambient temperature during Flash ROM programming 3 Digital power supply voltage during Flash ROM programming 3 VWR TWR CWR VDD 4 75 to 5 25 V Ta 40 to 90 C Ta 40 to 90 C VDD 4 75 to 5 25 V 4 75 to 5 25 40 to 90 100 cycle V C C 25 2 Operating Range MSM66591 1 fOSC is the frequency of the internal master clock ...

Page 446: ...age VOL IO 3 2 mA 0 4 1 4 L level output voltage IO 1 6 mA 0 4 2 Input leakage current Input leakage current IIH IIL 1 1 6 0 1 0 1 3 Input current VI VDD 0 V 1 250 µA 5 Input current 15 15 7 H level output current IOH VO 2 4 V 2 mA 1 4 H level output current 1 2 L level output current IOL 10 1 4 L level output current 5 2 Output leakage current ILO VO VDD 0 V 2 µA 1 2 4 Input capacity CI f 1 MHz T...

Page 447: ... Only for MSM66Q591 4 When programming data into Flash ROM using Oki s Flash ROM programmer or YDC s Flash ROM programmer use a resistor of 1 kΩ or less if connecting an external resistor in series with the TEST pin Apply a high voltage to the TEST or EA pin after a voltage within the range 4 75 to 5 25 V guaranteed for operation is applied to VDD Remove a high voltage from the TEST or EA pin whil...

Page 448: ... 3tøW 10 4tøW 3 High address hold time tAPH 0 tøW 10 Instruction setup time tIS Instruction hold time tIH 0 tøW 10 VDD 5 V 10 Ta 40 to 115 C 2 30 1 The master clock pulse is the frequency generated by multiplying the original oscillation clock by 2 2 If this device is used in circumstances where the ambient temperature Ta exceeds 85 C be sure to contact your local Oki sales office in advance Maste...

Page 449: ...urce impedance 10 Bit Resolution EL Linearity error ED Differential linearity error EZS LSB Zero scale error EFS Full scale error ECT Refer to the measurement circuit Figure 25 2 Crosstalk tCONV by ADTM set data 10 7 21 3 µs ch Conversion time Ta 40 to 115 C AVDD VDD VREF 5 V 10 AGND GND 0 V fOSC 24 MHz 1 2 RI 5 kW tCONV 16 µs 3 1 3 3 1 1 fOSC is the frequency of the internal master clock the mast...

Page 450: ...characteristics Ideally the range of analog input voltage that corresponds to 1 converted bit of digital output is 1LSB VREF AGND 1024 Differential error is the difference between this ideal bit size and bit size of an arbitrary point in the conversion range 4 Zero scale error Zero scale error is the difference between ideal conversion characteristics and actual conversion characteristics at the p...

Page 451: ...tage 2 Analog reference voltage Analog input voltage VREF VHV 0 3 to VDD 0 3 and 0 3 to AVDD 0 3 0 3 to 13 ML66592 Electrical Characteristics 25 6 Absolute Maximum Ratings ML66592 1 If this device is used in circumstances where the ambient temperature Ta exceeds 85 C be sure to contact your local Oki sales office in advance 2 Applied to TEST EA Only for ML66Q592 Apply a high voltage to the TEST or...

Page 452: ...perature Fanout MHz fOSC 0 Hz 1 VDD AVDD 20 MHz fOSC 28 MHz 1 Flash ROM programming cycle 3 Ambient temperature during Flash ROM programming 3 Digital power supply voltage during Flash ROM programming 3 VWR TWR CWR VDD 4 75 to 5 25 V Ta 40 to 90 C Ta 40 to 90 C VDD 4 75 to 5 25 V 4 75 to 5 25 40 to 90 100 cycle V C C 25 7 Operating Range ML66592 1 fOSC is the frequency of the internal master clock...

Page 453: ...ge VOL IO 3 2 mA 0 4 1 4 L level output voltage IO 1 6 mA 0 4 2 Input leakage current Input leakage current IIH IIL 1 1 6 0 1 0 1 3 Input current VI VDD 0 V 1 250 µA 5 Input current 15 15 7 H level output current IOH VO 2 4 V 2 mA 1 4 H level output current 1 2 L level output current IOL 10 1 4 L level output current 5 2 Output leakage current ILO VO VDD 0 V 2 µA 1 2 4 Input capacity CI f 1 MHz Ta...

Page 454: ... EA Only for ML66Q592 4 When programming data into Flash ROM using Oki s Flash ROM programmer or YDC s Flash ROM programmer use a resistor of 1 kΩ or less if connecting an external resistor in series with the TEST pin Apply a high voltage to the TEST or EA pin after a voltage within the range 4 75 to 5 25 V guaranteed for operation is applied to VDD Remove a high voltage from the TEST or EA pin wh...

Page 455: ...p time tIS Instruction hold time tIH 0 tøW 10 VDD 5 V 10 Ta 40 to 95 C 2 30 1 The master clock pulse is the frequency generated by multiplying the original oscillation clock by 2 2 If this device is used in circumstances where the ambient temperature Ta exceeds 85 C be sure to contact your local Oki sales office in advance 3 In the ML66Q592 the electrical characteristics for external memory access...

Page 456: ...ource impedance 10 Bit Resolution EL Linearity error ED Differential linearity error EZS LSB Zero scale error EFS Full scale error ECT Refer to the measurement circuit Figure 25 4 Crosstalk tCONV by ADTM set data 9 1 18 3 µs ch Conversion time Ta 40 to 95 C AVDD VDD VREF 5 V 10 AGND GND 0 V fOSC 28 MHz 1 2 RI 5 kW tCONV 18 3 µs 3 1 3 3 1 1 fOSC is the frequency of the internal master clock the mas...

Page 457: ...haracteristics Ideally the range of analog input voltage that corresponds to 1 converted bit of digital output is 1LSB VREF AGND 1024 Differential error is the difference between this ideal bit size and bit size of an arbitrary point in the conversion range 4 Zero scale error Zero scale error is the difference between ideal conversion characteristics and actual conversion characteristics at the po...

Page 458: ...Package Dimensions Chapter 26 26 ...

Page 459: ......

Page 460: ...fore you perform reflow mounting contact Oki s responsible sales person for the product name package name pin number package code and desired mounting conditions reflow method temperature and times 26 Package Dimensions LQFP144 P 2020 0 50 K Package material Lead frame material Pin treatment Rev No Last Revised Epoxy resin 42 alloy Solder plating 5 mm 5 Nov 28 1996 Package weight g 1 37 TYP Unit m...

Page 461: ...26 2 MSM66591 ML66592User sManual Chapter 26 Package Dimensions ...

Page 462: ...Revision History Chapter 27 27 ...

Page 463: ......

Page 464: ...27 1 MSM66591 ML66592User sManual Chapter 27 Revision History 27 27 Revision History Document No Date Page Description FEUL66591 66592 01 First edition Mar 4 2002 Previous Edition Current Edition ...

Page 465: ...27 2 MSM66591 ML66592User sManual Chapter 27 Revision History ...

Page 466: ...and intellectual property right etc is granted by us in connection with the use of the product and or the information and drawings contained herein No responsibility is assumed by us for any infringement of a third party s right which may result from the use thereof 6 The products listed in this document are intended for use in general electronics equipment for commercial applications e g office a...

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