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Octek Hippo-SX, Manual

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Octek Hippo-SX Manual Download Page 28

CONFIGURING THE SYSTEM
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DRAM CONFIGURATION

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Summary of Contents for Hippo-SX

Page 1: ...H I P P O S X...

Page 2: ...l in this manual is for information only and is subject to change without notice REVISION 1 0 IBM IBM PC XT AT PC DOS MS DOS OS 2 INTEL AMI ARE THE TRADEMARKS OR REGISTERED TRADEMARKS OF THEIR RESPECT...

Page 3: ...y from the receiver Move the computer away from the receiver Plug the computer into a different outlet so that computer and receiver are on different branch circuits Ensure that card slot covers are i...

Page 4: ...power make sure that all the connectors memory modules and add on cards are secured 3 After power is on wait for a minute The system BIOS are going through a self test during this period and nothing i...

Page 5: ...eers In this manual there are 4 chapters Chapter 1 contains a brief introduction In Chapter 2 the specification and functions of OCTEK Hippo SX motherboard are explained It also outlines many advanced...

Page 6: ...Memory 2 6 Memory System 2 8 Dual Bus Design 2 10 Chapter 3 CONFIGURING THE SYSTEM Installing Math Coprocessor 3 1 Installing RAM Modules 3 3 Configuration of Memory 3 5 DRAM Configuration 3 7 Control...

Page 7: ...MA 4 7 Real Time Clock and CMOS RAM 4 9 CMOS RAM Address Map 4 10 Real Time Clock Information 4 11 System Expansion Bus 4 12 Appendix A MEMORY EXPANSION CARD Appendix B HIPPO CACHE CARD Appendix C OPE...

Page 8: ...x D TROUBLESHOOTING Main Memory Error D 1 Cache Memory Failure D 1 Improper Setting of Wait State D 2 Appendix E SYSTEM BOARD LAYOUT Appendix F MEMORY EXPANSION CARD LAYOUT Appendix G HIPPO CACHE CARD...

Page 9: ...Hippo SX is suitable for those users who need power for the daily computing applications and network operations The burst read mode is supported and thus the data is transferred to CPU at full speed F...

Page 10: ...issues I O channel is compatible to standard AT bus Therefore any peripheral may be used on OCTEK Hippo SX On board POWERGOOD generator is essential to ensure the reliability of the system and is wel...

Page 11: ...ITEK 4167 Co processor Speed Turbo normal speed I O Slot Compatible to standard AT bus Eight 16 bit slots Optional Secondary Cache Memory 128KB Direct mapped Write through Memory Shadow RAM and Memory...

Page 12: ...port functions 8 Channel DMA Direct Memory Access 16 level interrupt 3 programmable timers CMOS RAM for system configuration Real time clock with battery back up Fast A20 gate and fast reset Other Fea...

Page 13: ...eparated from CPU CPU still needs to fetch code and data from external bus That means the data transfer rate should not be too fast to allow the external devices to keep pace with the CPU In 80486SX t...

Page 14: ...y improves the overall performance When the CPU writes data to the main memory the data is first stored in a write buffer There are four write buffers When the external bus is idle data will be sent t...

Page 15: ...concurrent operation and manipulating huge data base can be accomplished with excellent performance Paging mechanism is employed to allow powerful operating system to implement virtual memory Each se...

Page 16: ...fer The performance to a great extent depends on the data transfer rate In a 80486SX system a large portion of the internal cache memory has to be updated to the main memory and then the data for anot...

Page 17: ...y or more which means data of different processes can coexist in the secondary cache memory So an optimal size is 128K or 512K bytes and this size is adequate for over 8M bytes main memory In Hippo SX...

Page 18: ...The memory is divided into pages Successive memory accesses within the same page need not require wait state When more than one bank of memory are installed the page size is effectively increased beca...

Page 19: ...GENERAL FEATURES __________________________________ thus is available to software 1 256M 256KB 1M 1M 256KB 640K 640K 0K 0K before remapping after remapping Memory remapping...

Page 20: ...speed In Hippo SX a dual bus design is employed A high speed bus links the CPU coprocessor cache memory and main memory This bus is synchronous with clock of the CPU and the data transfer is 32 bits...

Page 21: ...GENERAL FEATURES __________________________________...

Page 22: ...he power before installing or replacing any component INSTALLING MATH COPROCESSOR Math coprocessor WEITEK 4167 is a PGA devices Beside the CPU there is a 144 pin PGA socket To install Math Coprocessor...

Page 23: ...nstalling the Math coprocessor make sure that all the pins are straight The pins are very fragile Once these pins are bent the coprocessor may be damaged The Math coprocessor is automatically detected...

Page 24: ...sockets for SIMM modules Whenever you add memory to the motherboard install four modules at the same time Also make sure that the chips on the modules face towards CPU The modules should be locked by...

Page 25: ...d to be in vertical position and should be dragged out and re inserted again Do not force the module into the SIMM socket It will damage the locking latches The modules should be locked by the locking...

Page 26: ...for those banks with similar pairs or quartet of DRAMs The memory size is detected automatically by system BIOS and indicated during memory test after reset No jumper is needed to be set for the memo...

Page 27: ...f memory remapping is disabled the BIOS will show 640KB After enabled the memory size is increased to 896KB The rest of the memory 128KB is assigned for shadow RAM and can not be used by software The...

Page 28: ...6K 4M 4W 6 1M 0 0 0 4M 7 256K 1M 0 0 5M 8 1M 256K 0 0 5M 9 256K 256K 1M 0 6M 2W 10 256K 1M 256K 0 6M 11 1M 256K 256K 0 6M 12 256K 256K 1M 256K 7M 2W 13 256K 1M 256K 256K 7M 2W 14 1M 256K 256K 256K 7M...

Page 29: ...CONFIGURING THE SYSTEM __________________________________ 25 1M 1M 1M 256K 13M 2W 26 1M 256K 1M 1M 13M 2W 27 1M 1M 1M 1M 16M 4W 28 4M 16M 29 4M 4M 32M 2W...

Page 30: ...the system malfunction In this case turn off the power and set JP1 to 1 2 for a while The internal CMOS status register is reset Then set the jumper to 2 3 and turn on the power The BIOS finds the CM...

Page 31: ...ER SETTING There are several options which allows user to select by hardware switches JP3 and JP4 are reserved Display Selection JP2 ON CGA EGA VGA OFF Monochrome display Secondary Cache Installation...

Page 32: ...unctions of connectors on the version 2 0 motherboard are listed below Connector Function SW1 Hardware reset connector J26 Speaker connector J27 Power LED Ext lock connector J11 J12 Power supply conne...

Page 33: ...___ J 1 External Battery Connector Pin Assignment 1 Vdc 2 not used 3 Ground 4 Ground J 2 Keyboard Connector Pin Assignment 1 Keyboard clock 2 Keyboard data 3 Spare 4 Ground 5 5 Vdc J 26 Speaker Connec...

Page 34: ...CONFIGURING THE SYSTEM __________________________________...

Page 35: ...27 Power LED Ext Lock Connector Pin Assignment 1 5 Vdc 2 Key 3 Ground 4 Keyboard inhibit 5 Ground J 11 J 12 Power Supply Connector Pin Assignment 1 POWERGOOD 2 5 Vdc 3 12 Vdc 4 12 Vdc 5 Ground 6 Grou...

Page 36: ...CONFIGURING THE SYSTEM __________________________________ 6 5 Vdc...

Page 37: ...SX MEMORY MAPPING Address Range Function 000000 7FFFFF 000K 512K System Board Memory 512K 080000 09FFFF 512K 640K System Board Memory 128K 0A0000 0BFFFF 640K 768K Display Buffer 128K 0C0000 0DFFFF 76...

Page 38: ...HEX DEVICE 000 01F DMA Controller 1 8237 020 03F Interrupt Controller 1 8259 Master 040 05F Timer 8254 060 06F Keyboard Controller 070 07F Real Time Clock NMI non maskable interrupt mask 080 09F DMA...

Page 39: ...sk 200 207 Game I O 278 27F Parallel Printer Port 2 2F8 2FF Serial Port 2 300 31F Prototype Card 360 36F Reserved 378 37F Parallel Printer Port 1 380 38F SDLC bisynchronous 2 3A0 3AF Bisynchronous 1 3...

Page 40: ...three programmable timer counters controlled by 82C206 and they are defined as channels 0 through 2 Channel 0 System Timer Gate 0 Tied on Clk in 0 1 190 Mhz OSC Clk out 0 8259 IRQ 0 Channel 1 Refresh...

Page 41: ...I bit Clk in 2 1 190 Mhz OSC Clk out 2 Used to drive the speaker Note Channel 1 is programmed to generate a 15 micro second period signal The 8254 Timer Counters are treated by system programs as an a...

Page 42: ...ocessor NMI Parity or I O Channel Check Interrupt Controllers CTLR 1 CTLR 2 IRQ0 Timer Output 0 IRQ1 Keyboard Output Buffer Full IRQ2 Interrupt from CTLR 2 IRQ8 Real time Clock Interrupt IRQ9 Software...

Page 43: ...TECHNICAL INFORMATION __________________________________...

Page 44: ...ACCESS DMA OCTEK Hippo SX supports seven DMA channels Channel Function 0 Spare 8 bit transfer 1 SDLC 8 bit transfer 2 Floppy Disk 8 bit transfer 3 Spare 8 bit transfer 4 Cascade for DMA Controller 1 5...

Page 45: ...____________ The following shows the addresses for the page register Page Register I O Address HEX DMA Channel 0 0087 DMA Channel 1 0083 DMA Channel 2 0081 DMA Channel 3 0082 DMA Channel 5 008B DMA Ch...

Page 46: ...ND CMOS RAM Real time clock and CMOS RAM are contained on board Real time clock provides the system date and time CMOS RAM stores system information Both are backed up by battery and will not lose inf...

Page 47: ...rive type byte drives A and B 11 Reserved 12 Fixed disk type byte drives C and D 13 Reserved 14 Equipment byte 15 Low base memory byte 16 High base memory byte 17 Low expansion memory byte 18 High exp...

Page 48: ...real time clock bytes and specifies their addresses Byte Function Address 0 Seconds 00 1 Second alarm 01 2 Minutes 02 3 Minute alarm 03 4 Hours 04 5 Hour alarm 05 6 Day of week 06 7 Date of month 07 8...

Page 49: ...___ SYSTEM EXPANSION BUS OCTEK Hippo SX provides eight 16 bit slots The I O channel supports I O address space from hex 100 to hex 3FF Selection of data access either 8 or 16 bit 24 bit memory address...

Page 50: ...TECHNICAL INFORMATION __________________________________ The following figure shows the pin numbering for I O channel connectors side A and B...

Page 51: ...TECHNICAL INFORMATION __________________________________ The following figure shows the pin numbering for I O channel connectors side C and D...

Page 52: ...onnectors I O Channel A Side I O Pin Signal Name I O A1 I O CH CK I A2 SD7 I O A3 SD6 I O A4 SD5 I O A5 SD4 I O A6 SD3 I O A7 SD2 I O A8 SD1 I O A9 SD0 I O A10 I O CH RDY I A11 AEN O A12 SA19 I O A13...

Page 53: ...TECHNICAL INFORMATION __________________________________ A23 SA8 I O A24 SA7 I O A25 SA6 I O A26 SA5 I O A27 SA4 I O A28 SA3 I O A29 SA2 I O A30 SA1 I O A31 SA0 I O...

Page 54: ...D Ground B2 RESET DRV I B3 5 Vdc Power B4 IRQ9 I B5 5 Vdc Power B6 DRQ2 I B7 12 Vdc Power B8 0WS I B9 12 Vdc Power B10 GND Ground B11 SMEMW O B12 SMEMR O B13 IOW I O B14 IOR I O B15 DACK3 I B16 DRQ3 O...

Page 55: ...TECHNICAL INFORMATION __________________________________ B26 DACK2 O B27 T C O B28 BALE O B29 5 Vdc Power B30 OSC O B31 GND Ground...

Page 56: ...Channel C Side I O Pin Signal Name I O C1 SBHE I O C2 LA23 I O C3 LA22 I O C4 LA21 I O C5 LA20 I O C6 LA19 I O C7 LA18 I O C8 LA17 I O C9 MEMR I O C10 MEMW I O C11 SD8 I O C12 SD9 I O C13 SD10 I O C14...

Page 57: ...O Channel D Side I O Pin Signal Name I O D1 MEM CS16 I D2 I O CS16 I D3 IRQ10 I D4 IRQ11 I D5 IRQ12 I D6 IRQ15 I D7 IRQ14 I D8 DACK0 O D9 DRQ0 I D10 DACK5 O D11 DRQ5 I D12 DACK6 O D13 DRQ6 I D14 DACK...

Page 58: ...l determine the type of DRAM and the amount of total memory There is no need to set any jumper The system BIOS will prompt you to setup the memory size after re boot However you should make sure that...

Page 59: ...THIS PAGE IS INTENTIONALLY LEFT BLANK...

Page 60: ...below 1 Turn off the power and plug in the card 2 Turn on the power and enter CMOS SETUP 3 Enable the cache memory 4 Turn off the power again and then remove the mini jumper on JP5 and JP6 5 Turn on...

Page 61: ...THIS PAGE IS INTENTIONALLY LEFT BLANK...

Page 62: ...golden finger Hold the cards by their edges KEEPING THE SYSTEM COOL The motherboard contains many high speed components and they will generate heat during operation Other add on cards and hard disk dr...

Page 63: ...the add on card may not work properly Use a pencil eraser to clean the golden finger if dirt is found CLEANING THE MOTHERBOARD The computer system should be kept clean Dust and dirt are harmful to el...

Page 64: ...d will not be counted by the BIOS It is also a memory failure and you can follow the instruction above CACHE MEMORY FAILURE If the system hangs after memory test it is likely that the cache memory has...

Page 65: ...s after memory test another possible cause is the improper setting of the wait state for memory operation The number of wait state must match the speed of the DRAM Reset the CMOS RAM and set up the wa...

Page 66: ...Appendix E System Board Layout _______________________________...

Page 67: ...Appendix F Memory Expansion Card Layout _______________________________...

Page 68: ...Appendix G Hippo Cache Card Layout _______________________________...

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