Octek Hippo-SX, Manual

Page: 20 / 68

GENERAL FEATURES
__________________________________
DUAL BUS DESIGN
It is very important that a high speed system
should be compatible with existing peripherals without
lowering the performance. To be compatible, the I/O slot
should run at 8MHz or slower. On the other hand, the
rest of the system are running at full speed.
In Hippo-SX, a dual bus design is employed. A
high speed bus links the CPU, coprocessor, cache
memory and main memory. This bus is synchronous with
clock of the CPU and the data transfer is 32 bits.
Whenever there is a request for transferring data to or
from I/O slot, the chipset is responsible for handling the
conversion between the bus. The clock rate of the high
speed bus will not be reduced, which eliminates many
compatibility problem.
CPU
High Speed
bus 8Mhz bus
Chip Set I/O Slot
Cache Main
Memory Memory
┌─────┐
│ │
└──┬──┘
│ ┌───────┐ ┌───────┐
├───────┬────┤ ├──────┤ │
│ │ └───────┘ └───────┘
│ │
┌──┴───┐┌──┴───┐