To select the specific CD4051 to be enabled, the CPU addresses one of
the 16 locations on CD4515 U15, which is a 4-to-16 decoder whose
outputs are normally high. When addresses, the output goes low,
enabling one of the 16 CD4051s memory mapped into the system. The
particular CD4051 connected to each output enable pin is labeled on
U15.
Note that ENABLE 14 is split into EN14 L (left) and EN14 R (right). This
is because the ADSR1 enables (EN14) are split onto VCF Card L and
VCF Card R.
5.3
Modulation System Scan Clocks
The mod system scans at a rate that is totally independent of the CPU
address/data lines. The clocks for this system are generated by CD4093
U17, CD4520 U9 and CD4013 U10. CD4093 is a quad Schmitt NAND
gate which is used as an astable multivibrator oscillating at
approximately 500 kHz. The frequency accuracy is insignificant and
deviations of up to 20% are acceptable. This clock output is divided down
by the synchronous counter CD4520, whose outputs are used as
address clocks for the modulation system. Whenever a symbol preceded
by an
M
is encountered in the VOYETRA logic description (
e.g.
, MA0) it
stands for “modulation system signal.” Thus, MA0, MA1 and MA2 are the
modulation system address lines which are periodic square waves. The
line labeled MODEN (MODULATION ENABLE) is a shifted enable pulse
used to enable demultiplexing CD4051s in the modulation system.
5.4
Demultiplexing / Remultiplexing
The unconventional configuration of CD4051 U18 and U28 followed by
CD4052 U19 and U25 are consequences of the modulation system
design. The mod system uses the Velocity signals demultiplexed at the
outputs of U27 and the ADSR signals demultiplexed at the outputs of
U18. However, as explained in the mod system theory section, the scan
rate of these signals is fixed by the modulation system. Thus, the CPU
generates signals at the CD4051 outputs that look like normal individual
voice signal, while the CD4052 at the outputs remultiplex the signals into
two groups of four voices for the left and right sides of the system.
With this in mind, note that the address and enable lines on the CD4051s
which are controlled by the CPU will be erratic, unsyncable signals while
the clocks on the CD4052 (which are controlled by the modulation
system clocks) are periodic stable square waves.
