NXP Semiconductors TWR-SER2, User Manual

Page: 15 / 17

TWR-SER2 User’s Manual Page 15 of 17
4 Configuration Settings
There are several jumpers provided for isolation, configuration, and feature selection. Refer to the
following table for details. The default installed jumper settings are shown in *
bold *.
4.1 Switch Settings
Switch Options Setting Description
SW1
Eth
e
rn
e
t
Stra
p
p
in
g
F
u
n
c
ti
o
n
s
/
Se
tt
in
g
s
Dip 1
*On* Enables RMII mode for Ethernet PHY A
Off Enables MII mode for Ethernet PHY A
Dip 2
*On* Connects RX_CRS to RMII0_CRS_DV (required for RMII operation)
Off Disconnects RX_CRS from RMII0_CRS_DV (required for MII operation)
Dip 3
On Connects RX_CRS to MII_CRS (required for MII operation)
*Off* Disconnects RX_CRS from MII_CRS (required for RMII operation)
Dip 4
On Connects RX_DV to MII_RXDV (required for MII operation)
*Off* Disconnects RX_DV from MII_RXDV (required for RMII operation)
Dip 5
On Enables Dual PHY Extender Mode
*Off* Disables Extender Mode
Dip 6
On PHY A - Auto Negotiation (Use AN0/AN1 to set highest capability)
*Off* PHY A - Forced Mode (Use AN0/AN1 to set forced mode)
Dip 7
On AN0_A - Full-Duplex on PHY A
*Off*
AN0_A - Half-Duplex on PHY A
Dip 8
On AN1_A - 100Base-TX on PHY A
*Off* AN1_A - 10Base-T on PHY A
SW2
Eth
e
rn
e
t
Stra
p
p
in
g
F
u
n
c
ti
o
n
s
/
Se
tt
in
g
s
Dip 1
*On* Enables RMII mode for Ethernet PHY B
Off Enables MII mode for Ethernet PHY B
Dip 2
On Connects CLOCKOUT0 to Ethernet PHY Clock
*Off* Isolates CLOCKOUT0 from Ethernet PHY Clock
Dip 3
*On* Connects onboard 50MHz clock to Ethernet PHY Clock
Off Isolates onboard 50MHz clock from Ethernet PHY Clock
Dip 4
On Connects onboard 25MHz clock to Ethernet PHY Clock
*Off*
Isolates onboard 25MHz clock from Ethernet PHY Clock
Dip 5
On Disables onboard 25MHz / 50MHz clock
*Off* Enables onboard 25MHz / 50MHz clock
Dip 6
On PHY B - Auto Negotiation (Use AN0/AN1 to set highest capability)
*Off* PHY B - Forced Mode (Use AN0/AN1 to set forced mode)
Dip 7
On AN0_B - Full-Duplex on PHY B
*Off* AN0_B - Half-Duplex on PHY B
Dip 8
On AN1_B - 100Base-TX on PHY B
*Off* AN1_B - 10Base-T on PHY B
Figure 3 - TWR-SER2 Switch Settings