background image

 
 
 

 

 

TWR-SER2 User’s Manual 

Page 14 of 17 

 

TWR-SER2 Secondary Connector 

Pin 

Name 

Usage 

Used 

Jmp 

Pin 

Name 

Usage 

Used  Jmp 

D43 

LCD_CONTRAST 

 

 

 

C43 

UART2_RTS / TSI2 

UART2_RTS 

D44 

LCD_OE / LCD_P27 

 

 

 

C44 

UART2_CTS / TSI3 

UART2_CTS 

D45 

LCD_D0 / LCD_P0 

 

 

 

C45 

UART3_RXD / TSI4 

UART3_RX 

D46 

LCD_D1 / LCD_P1 

 

 

 

C46 

UART3_TXD / TSI5 

UART3_TX 

D47 

LCD_D2 / LCD_P2 

 

 

 

C47 

UART3_RTS / CAN3_RX 

UART3_RTS 

D48 

LCD_D3 / LCD_P3 

 

 

 

C48 

UART3_CTS / CAN3_TX 

UART3_CTS 

D49 

GND 

Ground 

 

C49 

GND 

Ground 

 

D50 

GPIO23 

 

 

 

C50 

LCD_D4 / LCD_P4 

 

 

 

D51 

GPIO24 

 

 

 

C51 

LCD_D5 / LCD_P5 

 

 

 

D52 

LCD_D12 / LCD_P12 

 

 

 

C52 

LCD_D6 / LCD_P6 

 

 

 

D53 

LCD_D13 / LCD_P13 

 

 

 

C53 

LCD_D7 / LCD_P7 

 

 

 

D54 

LCD_D14 / LCD_P14 

 

 

 

C54 

LCD_D8 / LCD_P8 

 

 

 

D55 

IRQ_P / SPI2_CS2_b 

 

 

 

C55 

LCD_D9 / LCD_P9 

 

 

 

D56 

IRQ_O / SPI2_CS3_b 

 

 

 

C56 

LCD_D10 / LCD_P10 

 

 

 

D57 

IRQ_N 

 

 

 

C57 

LCD_D11 / LCD_P11 

 

 

 

D58 

IRQ_M 

 

 

 

C58 

I2S1_DIN_SCK 

 

 

 

D59 

IRQ_L 

 

 

 

C59 

I2S1_DIN_WS 

 

 

 

D60 

IRQ_K 

 

 

 

C60 

I2S1_DIN1 

 

 

 

D61 

IRQ_J 

 

 

 

C61 

I2S1_DOUT1 

 

 

 

D62 

IRQ_I 

 

 

 

C62 

LCD_D15 / LCD_P15 

 

 

 

D63 

LCD_D18 / LCD_P18 / SD_RX_0 

 

 

 

C63 

LCD_D16 / LCD_P16 / SD_GND 

 

 

 

D64 

LCD_D19 / LCD_P19 / SD_RXb_0 

 

 

 

C64 

LCD_D17 / LCD_P17 / SD_GND 

 

 

 

D65 

GND 

Ground 

 

C65 

GND 

Ground 

 

D66 

EBI_AD20 / LCD_P42 / SD_GND 

 

 

 

C66  EBI_BE_32_24_b / LCD_P28 / SD_TX_0 

 

 

 

D67 

EBI_AD21 / LCD_P43 / SD_GND 

 

 

 

C67 

EBI_BE_23_16_b / LCD_P29 / 

SD_TXb_0 

 

 

 

D68 

EBI_AD22 / LCD_P44 / SD_RX_1 

 

 

 

C68 

EBI_BE_15_8_b / LCD_P30 / SD_GND 

 

 

 

D69  EBI_AD23 / LCD_P45 / SD_RXb_1 

 

 

 

C69 

EBI_BE_7_0_b / LCD_P31 / SD_GND 

 

 

 

D70 

EBI_AD24 / LCD_P46  / SD_GND 

 

 

 

C70 

EBI_TSIZE0 / LCD_P32 / SD_TX_1 

 

 

 

D71 

EBI_AD25 / LCD_P47 / SD_GND 

 

 

 

C71 

EBI_TSIZE1 / LCD_P33 / SD_TXb_1 

 

 

 

D72 

EBI_AD26 / LCD_P48 / SD_RX_2 

 

 

 

C72 

EBI_TS_b / LCD_P34 / SD_GND 

 

 

 

D73  EBI_AD27 / LCD_P49 / SD_RXb_2 

 

 

 

C73 

EBI_TBST_b / LCD_P35 / SD_GND 

 

 

 

D74 

EBI_AD28 / LCD_P50 / SD_GND 

 

 

 

C74 

EBI_TA_b / LCD_P36 / SD_TX_2 

 

 

 

D75 

EBI_AD29 / LCD_P51 / SD_GND 

 

 

 

C75 

EBI_CS4_b / LCD_P37 / SD_TXb_2 

 

 

 

D76 

EBI_AD30 / LCD_P52 / SD_RX_3 

 

 

 

C76 

EBI_CS3_b / LCD_P38 / SD_GND 

 

 

 

D77  EBI_AD31 / LCD_P53 / SD_RXb_3 

 

 

 

C77 

EBI_CS2_b / LCD_P39 / SD_GND 

 

 

 

D78 

LCD_D20 / LCD_P20 / SD_GND 

 

 

 

C78 

EBI_CS1_b / LCD_P40 / SD_TX_3 

 

 

 

D79  LCD_D21 / LCD_P21 / SD_REFCLK 

 

 

 

C79 

GPIO31 / LCD_P41 / SD_TXb_3 

 

 

 

D80 

LCD_D22 / LCD_P22 / 

SD_REFCLKb 

 

 

 

C80 

LCD_D23 / LCD_P23 / SD_GND 

 

 

 

D81 

GND 

Ground 

 

C81 

GND 

Ground 

 

D82 

3.3V 

3.3V Power 

 

C82 

3.3V 

3.3V Power 

 

 
 

Summary of Contents for TWR-SER2

Page 1: ...Freescale Semiconductor Inc TWR SER2 User s Manual Rev 1 2...

Page 2: ...net PHYs 6 3 3 Hi Speed Dual Role USB 6 3 4 Low Full Speed Host USB 7 3 5 Serial Communications Interface 7 3 5 1 RS 232 485 Interface 7 3 5 2 Serial to USB 8 3 5 3 Additonal RS232 Interfaces 8 3 6 CA...

Page 3: ...ade Dual Ethernet PHY Transceiver w dual RJ 45 Ethernet Jacks with integrated magnetics and LED s Industrial grade High Speed Dual Role USB PHY utilizes MPU s ULPI interface Full Speed Low Speed Host...

Page 4: ...S16 USB mini B Serial COM Intersil ICL3225 RS 232 Intersil ISL3176 RS 485 Selection Isolation Jumpers RS 232 RS 485 Intersil ICL3225 RS 232 Intersil ICL3225 RS 232 2x5 Header 2x5 Header Isolation Jump...

Page 5: ...the latest revision of all released Tower documentation TWR SER2 Schematics TWR SER2 Quick Start Guide Freescale MC9S08JS16 Microcontroller with integrated USB Transceiver DP83849I PHYTER DUAL Industr...

Page 6: ...RMII interfaces The Ethernet PHY is configurable via two sets of micro dip switches SW1 and SW2 Refer to these settings for typical Ethernet setting For specific setting details refer to the TWR SER2...

Page 7: ...ce UART1 RXD TXD is connected to both an RS 232 transceiver and an RS 485 transceiver selectable by a series of selection jumpers J1 J2 J13 The RS 232 and RS 485 transceivers are terminated at a commo...

Page 8: ...CD and is also available on the TWR SER2 webpage found at www freescale com tower If needed the UART0 transceiver signals can be isolated from the Tower Elevator using J7 Pins Description 1 2 Remove t...

Page 9: ...n be connected to the Tower Elevator connector using J22 and J23 respectively Pins Description 1 2 Remove to Isolate UARTx_TX 3 4 Remove to Isolate UARTx_RX 5 6 Remove to Isolate UARTx_RTS 7 8 Remove...

Page 10: ...Usage Used Jmp Pin Name Usage Used Jmp B1 5V 5 0V Power X A1 5V 5 0V Power X B2 GND Ground X A2 GND Ground X B3 3 3V 3 3V Power X A3 3 3V 3 3V Power X B4 ELE_PS_SENSE Elevator Power Sense X A4 3 3V 3...

Page 11: ...RT0_RX UART0_RX X X B42 CAN0_TX CAN_TX X X A42 UART0_TX UART0_TX X X B43 1WIRE CAN_S X X A43 UART1_RX UART1_RX X X B44 SPI0_MISO IO1 X A44 UART1_TX UART1_TX X X B45 SPI0_MOSI IO0 X A45 VSSA B46 SPI0_C...

Page 12: ...A68 EBI_AD12 B69 EBI_AD18 A69 EBI_AD11 B70 EBI_AD19 A70 EBI_AD10 B71 EBI_R W_b A71 EBI_AD9 B72 EBI_OE_b A72 EBI_AD8 B73 EBI_D7 A73 EBI_AD7 B74 EBI_D6 A74 EBI_AD6 B75 EBI_D5 A75 EBI_AD5 B76 EBI_D4 A76...

Page 13: ...C18 GPIO28 SDHC_D7 D19 ETH_TXD1 RMII1_TXD1 X C19 ETH_RXD1 RMII1_RXD1 X D20 ETH_TXD0 RMII1_TXD0 X C20 ETH_RXD0 RMII1_RXD0 X D21 ULPI_NEXT USB_HS_DM ULPI_NXT X C21 ULPI_DATA0 I2S1_MCLK ULPI_DATA0 X D22...

Page 14: ..._RX_0 C63 LCD_D16 LCD_P16 SD_GND D64 LCD_D19 LCD_P19 SD_RXb_0 C64 LCD_D17 LCD_P17 SD_GND D65 GND Ground X C65 GND Ground X D66 EBI_AD20 LCD_P42 SD_GND C66 EBI_BE_32_24_b LCD_P28 SD_TX_0 D67 EBI_AD21 L...

Page 15: ...e Dip 6 On PHY A Auto Negotiation Use AN0 AN1 to set highest capability Off PHY A Forced Mode Use AN0 AN1 to set forced mode Dip 7 On AN0_A Full Duplex on PHY A Off AN0_A Half Duplex on PHY A Dip 8 On...

Page 16: ...t A 1 2 Disables Ethernet PHY A J11 RS485 Config UART 1 1 2 Loopback Mode connects RE to DE 3 4 Loopback Mode connects TX0_P to RX0_P 5 6 Loopback Mode connects TX0_N to RX0_N 7 8 NC 9 10 5V Supply to...

Page 17: ...heral and complies with the electrical and mechanical specification as described in Freescale Tower Electromechanical Specification Freescale and the Freescale logo are trademarks of Freescale Semicon...

Reviews: