NXP Semiconductors PXN2020, Reference Manual, Page: 827 / 1376

Enhanced Modular Input/Output Subsystem (eMIOS200)
PXN20 Microcontroller Reference Manual, Rev. 1
Freescale Semiconductor 28-5
accumulation (PEC, PEA) and Quadrature Decode (QDEC). On the PXN21, five of these channels are
implemented on the device. On the PXN20, four of these channels are implemented.
28.1.4.2 Type B: Complex Channels
These complex channel types offer most of the modes already available on the counter channels. This
channel type includes Center aligned PWM modes with deadtime to allow support for motor control
applications, and may be combined with the quadrature decode of Type A channels. This channel type also
supports the lighting OPWMT mode, to add to the number of channels able to support this function as high
end BCM controllers need many of these channel types. Eight of these channels are implemented on both
versions of the PXN20 device.
28.1.4.3 Type C: Lighting Channels
The majority of the timer channels are implemented using this type of channel. Its prime role is support
for lighting control with the provision of the OPWMT mode, but also allows some other simple timed I/O
functionality to be provided. On the PXN21, 19 of these channels are implemented on the device. On the
PXN20, 12 of these channels are implemented.
Table 28-1. Supported Modes on PXN20 eMIOS Modules
Description Name
Channel Type
Number
Supported
Section/Page
Type A Type B Type C PXN21 PXN20
General Purpose Input / Output GPIO X X X 32 24 28.4.1.1.1/28-22
Single Action Input Capture SAIC X X X 32 24 28.4.1.1.2/28-23
Single Action Output Compare SAOC X X X 32 24 28.4.1.1.3/28-24
Input Pulse-Width Measurement IPWM X X X 32 24 28.4.1.1.4/28-25
Input Period Measurement IPM X X X 32 24 28.4.1.1.5/28-27
Double Action Output Compare DAOC X X X 32 24 28.4.1.1.6/28-29
Pulse Edge Accumulation PEA X — — 5 4 28.4.1.1.7/28-31
Pulse Edge Counting PEC X — — 5 4 28.4.1.1.8/28-32
Quadrature Decode QDEC X — — 5 4 28.4.1.1.9/28-34
Modulus Counter MC X X — 13 12 28.4.1.1.10/28-35
Modulus Counter Buffered (Up / Down) MCB X X — 13 12 28.4.1.1.11/28-37
Output Pulse Width and Frequency Modulation Buffered OPWFMB X X — 13 12 28.4.1.1.12/28-40
Center-Aligned Output PWM Buffered with Dead Time OPWMCB X X — 13 12 28.4.1.1.13/28-45
Output Pulse Width Modulation Buffered OPWMB X X X 32 24 28.4.1.1.14/28-50
Output Pulse Width Modulation Trigger OPWMT X X X 32 24 28.4.1.1.15/28-53
Input Filter IPF X X X 32 24 28.4.1.2/28-57