NXP Semiconductors PXN2020, Reference Manual, Page: 849 / 1376

Enhanced Modular Input/Output Subsystem (eMIOS200)
PXN20 Microcontroller Reference Manual, Rev. 1
Freescale Semiconductor 28-27
Figure 28-21. B1 and A1 Updates at EMIOS_CADR[n] and EMIOS_CBDR[n] Reads
Reading EMIOS_CADR[ n ] followed by EMIOS_CBDR[ n ] always provides coherent data. If no coherent
data is required, the sequence of reads should be inverted, therefore EMIOS_CBDR[ n ] should be read
prior to EMIOS_CADR[ n ] register. Even in this case B1 register updates are blocked after
EMIOS_CADR[ n ] is read, therefore a second EMIOS_CBDR[ n ] is required to release the B1 register
updates.
28.4.1.1.5 Input Period Measurement (IPM) Mode
The IPM mode (MODE = 000_0101) allows the measurement of the period of an input signal by capturing
two consecutive rising edges or two consecutive falling edges. Successive input captures are done on
consecutive edges of the same polarity. The edge polarity is defined by the EDPOL bit in the
EMIOS_CCR[
n ] register.
When the first edge of selected polarity is detected, the selected time base is latched into the registers A2
and B2, and the data previously held in register B2 is transferred to register B1. On this first capture the
FLAG line is not set and the values in registers B1 are meaningless. On the second and subsequent
captures, the FLAG line is set and data in register B2 is transferred to register B1.
When the second edge of the same polarity is detected, the counter bus value is latched into registers A2
and B2, and the data previously held in register B2 is transferred to data register B1 and to register A1.
The FLAG bit is set to indicate that the start and end points of a complete period have been captured. This
sequence of events is repeated for each subsequent capture. Registers EMIOS_CADR[
n ] and
EMIOS_CBDR[ n ] return the values in register A2 and B1, respectively.
To allow coherent data, reading EMIOS_CADR[ n ] forces A1 content be transferred to B1 register and
disables transfers between B2 and B1. These transfers are disabled until the next read of the
EMIOS_CBDR[
n ] register. Reading EMIOS_CBDR[ n ] register forces A1 content to be transferred to B1
and re-enables transfers from B2 to B1, to take effect at the next edge capture.
0x000500 0x001000 0x001100 0x001250 0x001525 0x0016A0
Selected
Counter Bus
FLAG
Set Event
B B B
A2 (Captured)
Value
2
0xxxxxxx
Notes:
1
After input filter
2
EMIOS_CADR[n] = A2
Input Signal
1
EDPOL = 1 A A
B1 Value
3
0x001525 0x001100
0xxxxxxx
0xxxxxxx
0x001000 0x001250 0x0016A0
0x001250 0x001000
B2 (Captured)
Value
3
EMIOS_CBDR[n] = B1
0xxxxxxx 0x001250 0x001000
A1 Value
3
0x001000
Read EMIOS_CADR[ n ] Read EMIOS_CBDR[ n ]