NXP Semiconductors PXN2020, Reference Manual, Page: 879 / 1376

Enhanced Modular Input/Output Subsystem (eMIOS200)
PXN20 Microcontroller Reference Manual, Rev. 1
Freescale Semiconductor 28-57
Figure 28-54. OPWMT with 100% Duty Cycle
28.4.1.2 Input Programmable Filter (IPF)
The IPF ensures that only valid input pin transitions are received by the unified channel edge detector. A
block diagram of the IPF is shown in
Figure 28-55 .
The IPF is a 5-bit programmable up counter that is incremented by the selected clock source, according to
IF bits in EMIOS_CCR[
n ].
Figure 28-55. lnput Programmable Filter Submodule Diagram
The input signal is synchronized by system clock. When a state change occurs in this signal, the 5-bit
counter starts counting up. As long as the new state is stable on the pin, the counter remains incrementing.
If a counter overflow occurs, the new pin value is validated. In this case, it is transmitted as a pulse edge
to the edge detector. If the opposite edge appears on the pin before validation (overflow), the counter is
reset. At the next pin transition, the counter starts counting again. Any pulse that is shorter than a full range
of the masked counter is regarded as a glitch and it is not passed on to the edge detector.
Figure 28-56
shows a timing diagram of the input filter.
0x0011FF
0x001000
0x000000
Selected Counter Bus
Time
Output Flip-Flop
A1 Value
1
write to B2
0x000400
B1 Value
B2 Value
2
0x001200
Match B1 does not occur
write to A1
0xxxxxxx
0x000400
0x001000
and B2
0x001000
Match A1
Match B1 Match A1
Notes:
1. EMIOS_CADR[n] = A1
2. EMIOS_CBDR[n] = B2 for write, B1 for read
0x001200
A2 Value 0x000500
0x000500
FLAG Pin/Register
Match A2
Match A2
Synchronizer
IF3
clk
IF2 IF1 IF0
5-bit Up Counter
FCK
Prescaled Clock
EMIOSI
Clock
ipg_clk
Filter Out