NXP Semiconductors P4080, User Manual, Page: 9 / 60

P4080 Development System User’s Guide, Rev. 0
Freescale Semiconductor 9
Architecture
5.1.1 DDR
The P4080 supports DDR2 and DDR3 devices; however, the P4080DS supports only DDR3 , using
industry-standard JEDEC DDR3 2-rank and 4-rank DIMM modules. However, the system is shipped and
supported by software to support UDIMM 2-rank modules for targeted vendors. The type and vendor may
change as memory availability varies. The memory interface includes all the necessary termination and
I/O power, and is routed so as to achieve maximum performance on the memory bus.
eOpenPIC Section 5.1.10, “eOpenPIC Interrupt Controller ”
GPIO Section 5.1.11, “GPIO Controller Port ”
System Control Section 5.1.12, “Control Group ”
UART Section 5.1.13, “UART Serial Ports ”
I2C Section 5.1.14, “I
2
C ”
EM1 and EM2 Management Section 5.1.15, “EM1 and EM2 Management Busses ”
Debug/Power Management Section 5.1.16, “Debug and Power Management ”
Clock Section 5.1.17, “Clock ”
Thermal Section 5.1.18, “Temperature ”
Power Section 5.1.19, “Power ”
Table 3. P4080 Pin Groupings Summary (continued)
Signal Group Details