NXP Semiconductors MPC8349E-mITX-GP, User Manual, Page: 27 / 36

MPC8349E-mITX-GP Reference Design Platform User’s Guide, Rev. 0
Freescale Semiconductor 27
Preliminary—Subject to Change Without Notice
MPC8349E-mITX-GP Board
Figure 20 shows the power supply block diagram.
Figure 20. Power Supply Circuitry
The core supply voltage and I/O supply voltages do not have to be applied in any particular order. During
the power ramp up, before the power supplies are stable, there may be an interval when the I/O pins are
actively driven. After power is stable, as long as PORESET is asserted, most I/O pins are three-stated. To
minimize the time I/O pins are actively driven, apply core voltage before I/O voltage and assert PORESET
before the power supplies fully ramp up. In general, for a dual-supply voltage device, minimize the voltage
difference between the V
core
and V
I/O
during ramp-up and power-down.
1.6.6 Chip-Select Assignments and Memory Map
Table 17 shows an example memory map on the MPC8349E that is used for u-boot 1.1.3 in the Flash
memory.
Table 17. Example Memory Map, Local Access Window, and Chip-Select Assignments
Address Range Target Interface
Chip-Select
Line
Device Name Port Size (Bits)
0x0000_0000–0x4000_0000 DDR MCS0/MCS1 DDR SDRAM (256 Mbytes– 1
Gbyte) 64
0x8000_0000–0x9FFF_FFFF PCI1 Nil PCI1 memory space (512 Mbyte) 32
0xE200_0000–0xE2FF_FFFF PCI1 Nil PCI1 I/O space (16 Mbyte) 32
0xA000_0000–0xBFFF_FFFF PCI2 Nil PCI2 memory space (512 Mbyte) 32
0xE300_0000–0xE3FF_FFFF PCI2 Nil PCI2 I/O space (16 Mbyte) 32
0xF000_0000–0xF000_FFFF Local bus LCS3 Reserved 8
0xF900_0000–0xF91F_FFFF Local bus LCS2 Reserved 8
0xF800_0000–0xF801_FFFF Local bus LCS1 Reserved 8
0xE000_0000–0xEFFF_FFFF Internal bus Nil IMMR (1 Mbyte) —
1.2 V
5 V input
2.5 V
MIC29302
3.3 V input
MAX1953
5 V
CPU Fan
3.3 V
MIC2505
5 V
USB VBUS Power
MPC8349E Vcore
DDR