NXP Semiconductors MPC8349E-mITX-GP User Manual Download Page 1

© Freescale Semiconductor, Inc., 2006. All rights reserved.

Preliminary—Subject to Change Without Notice

Freescale Semiconductor

User’s Guide

The MPC8349E-mITX-GP reference design platform is a 
system featuring the powerful PowerQUICC™ II Pro 
processor, which includes a built-in security accelerator. 
This low-cost, high-performance system solution consists of 
a printed circuit board (PCB) assembly known as the 
MPC8349E-mITX-GP Board, plus a board support package 
(BSP), distributed in a CD image. This BSP enables fastest 
possible time-to-market for development or integration of 
applications including media servers, network attached 
storage devices, and next-generation small office home 
office/small medium business gateways.

Section 1, “MPC8349E-mITX-GP Board,”

 describes the 

board in terms of its hardware: the features, specifications, 
block diagram, connectors, interface specification, and 
hardware straps.

Section 2, “Getting Started,” 

describes the board settings and 

physical connections needed to boot the 
MPC8349E-mITX-GP board. 

Section 3, “MPC8349E-mITX-GP Software,”

 describes the 

software that is shipped with the platform.

Use this manual in conjunction with the following 
documents:

MPC8349E PowerQUICC™ II Pro Integrated Host 
Processor Family Reference Manual
 
(MPC8349ERM)

Document Number: MPC8349EMITXGPUG

Rev. 0, 10/2006

Contents

1. MPC8349E-mITX-GP Board  . . . . . . . . . . . . . . . . . . .  2

2. Getting Started   . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  29

3. MPC8349E-mITX-GP Software . . . . . . . . . . . . . . . .  34

4. Revision History  . . . . . . . . . . . . . . . . . . . . . . . . . . . .  35

MPC8349E-mITX-GP Reference 
Design Platform User’s Guide

WARNING

This is a class A product. In a domestic 
environment this product may cause radio 
interference in which case the user may be 
required to take adequate measures. 

NOTE

This equipment has been tested and found to 
comply with the limits for a Class A digital 
device, pursuant to Part 15 of the FCC Rules. 
These limits are designed to provide 
reasonable protection against harmful 
interference when the equipment is operated 
in a commercial environment. This 
equipment generates, uses, and can radiate 
radio frequency energy and, if not installed 
and used in accordance with the instruction 
manual, may cause harmful interference to 
radio communications. Operation of this 
equipment in a residential area is likely to 
cause harmful interference in which case the 
user will be required to correct the 
interference at his own expense.

Summary of Contents for MPC8349E-mITX-GP

Page 1: ...e describes the software that is shipped with the platform Use this manual in conjunction with the following documents MPC8349E PowerQUICC II Pro Integrated Host Processor Family Reference Manual MPC8...

Page 2: ...ystem 128 MByte unbuffered DIMM SDRAM that is expandable to 1 Gbyte 8 MByte Flash memory one Macronix MX29LV640M Flash memory bankorone ESSI EN29LV640 Flash memory bank Interfaces 10 100 1000 BaseT Et...

Page 3: ...d in this section are reset interrupts and clock distribution 1 2 1 Reset and Reset Configurations The MPC8349E mITX GP reset module generates a single reset to reset the MPC8349E and other peripheral...

Page 4: ...vel and this meets the specification of the PORESET input of MPC834x COP JTAG port reset provides convenient hard reset capability for a COP JTAG controller The RESET line is available at the COP JTAG...

Page 5: ...errupt and connected to IRQ2 of the MPC8349E Therefore the system software can detect the status of the Ethernet link the PHY internal status and the RTC status PCI interrupt PCI_INTA PCI_INTB The 32...

Page 6: ...the clock distribution on the MPC8349E mITX GP board Figure 4 MPC8349E mITX GP Clock Scheme MPC8349E Local Bus CLK DDR SDRAM CLK LCLKx MCKx DS1339 GND GND 32 768 KHz Crystal MCKx 125 MHz 133 MHz 33 MH...

Page 7: ...the PCI_SYNC_OUT clock signal which is fed back on the board through the PCI_SYNC_IN signal to the internal system PLL From the power on reset configuration the CSB clock is generated by the internal...

Page 8: ...ace with the standard memory device an address latch must provide the address signals The LALE is used as the latching signal To reduce the load of the high speed 32 bit local bus interface there is a...

Page 9: ...rt size The starting address for the Flash bank is 0xFE00_0000 to 0xFE7F_FFFF 1 2 7 I2C The MPC8349E has two I2 C interfaces On the MPC8349E mITX GP board the MPC8349E acts as I2 C master for both I2C...

Page 10: ...umns the DDR timings e g CAS latency re fresh timing and setup the configuration registers of the MPC8349E DDR memory controller The I2 C address of the DDR SPD EEPROM on I2C2 bus is 0x51 There are tw...

Page 11: ...and receive clocks are generated by the VSC8201 PHY device The MPC8349E MII management interface is connected to the VSC8201 only Figure 7 shows the connection between the MPC8349E TSEC1 to the VSC820...

Page 12: ...SB1 a multi port host MPH module and a dual role DR module On the MPC8349E mITX GP board USB1 connects to USB PHY USB3300 through the 8 bit UTMI low pin count interface ULPI The USB3300 PHY connects t...

Page 13: ...PC8349E JTAG module and is implemented as a set of additional instructions and logic This port can connect to a dedicated emulator for extensive system debugging Several third party emulators in the m...

Page 14: ...B port emulator is shown in Figure 11 Figure 11 Connecting the MPC8349E mITX GP Board to A Parallel Emulator The 16 pin generic header connector carries the COP JTAG signals and the additional signals...

Page 15: ...section describes the MPC8349E mITX GP connectors and their pin assignments 1 4 1 Case Connector The case connector J10 connects to the case power switch power LED reset switch PWR_SW can connect to...

Page 16: ...sts the pin assignments of the COP connector 1 4 3 PCI Slot The MPC8349E mITX GP board has one 32 bit 3 3 V PCI expansion slot P1 for an expansion card WARNING Only the 3 3 V PCI Card is supported Tur...

Page 17: ...the other for powering a 12 V fan J5 For typical fans the red wire is always positive and the black wire is always negative 1 4 5 Battery Holder The MPC8349E mITX GP board contains an RTC that requir...

Page 18: ...Is On OFF Jumper Is Off Description A LGPL0 ON 0 000 local bus EEPROM Default 001 I2 C EEPROM PCI_CLK PCI_SYNC_IN 25 44 MHz 010 I2 C EEPROM PCI_CLK PCI_SYNC_IN 25 66 666 MHz 011 Hard coded option 66 M...

Page 19: ...are write protected Table 9 Lists of Connectors Jumpers Switches and LEDs Reference Description Connectors BT1 Battery holder for RTC J4 Background Debug Mode BDM Header for Flash programming and debu...

Page 20: ...neous board related data The EEPROM can be write protected by S2 SW3 as shown in Table 11 J19 CPU Power on reset source jumper CPU Power On Reset can be controlled by a hardware MAX811 reset chip jump...

Page 21: ...odes and endian mode The reset configuration word is divided into reset configuration word lower RCWL and reset configuration word higher RCWH and is loaded from the local bus during the power on or h...

Page 22: ...Field PCIHOST PCI64 PCI1ABR PCI2ABR COREDIS BMS BOOTSEQ SWEN ROMLOC 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Field TSEC1M TSEC2M TLE LALE LDP Figure 18 Reset Configuration Word High RCWH Bit Se...

Page 23: ...0 6 Value coreclk csb_clk VCO divider nn 0000 n PLL bypassed PLL bypassed 00 0001 0 1 1 2 01 0001 0 1 1 4 10 0001 0 1 1 8 11 0001 0 1 1 8 00 0001 1 1 5 1 2 01 0001 1 1 5 1 4 10 0001 1 1 5 1 8 11 0001...

Page 24: ...ault PCI2 arbiter enabled 3 Reserved Must be cleared 4 COREDIS Core disable mode 0 Default e300 enabled 1 e300 disabled 5 BMS Boot memory space 0 Default 0x0000_0000 0x007F_FFFF 1 0xFF80_0000 0xFFFF_F...

Page 25: ...1 2 lbiu_controller_clk earlier 30 LDP LDP CKSTP pin mux state after reset 0 Default LDP 0 and LDP 1 local data parity 1 LDP 0 CKSTOP_OUT and LDP 1 CKSTOP_IN 31 Reserved Must be cleared Table 16 Core...

Page 26: ...se uboot commands There is no change in the SPMF field since 0b0100 is the default value representing the 266 MHz CCB frequency The COREPLL field is changed from the default value of 0b000_0100 repres...

Page 27: ...core and VI O during ramp up and power down 1 6 6 Chip Select Assignments and Memory Map Table 17 shows an example memory map on the MPC8349E that is used for u boot 1 1 3 in the Flash memory Table 17...

Page 28: ...ypical Maximum 3 3 V DC 3 0 A 6 5 A 5 0 V DC 300 mA 2 0 A Communication processor MPC8349E running 533 MHz Addressing Total address range Flash memory local bus DDR SDRAM 4 Gbyte 32 address lines Up t...

Page 29: ...ensions of the MPC8349E mITX GP Board 2 Getting Started This section describes how to boot up the MPC8349E mITX GP board The on board Flash memory has been preloaded with a Flash image from the factor...

Page 30: ...marked for each reference Using Figure 22 as a guide the default jumper settings are given in Table 19 starting at the left hand top corner of the board and moving around the board in a clockwise mann...

Page 31: ...ype and various SDRAM configurations and timing parameters WARNING Switch the power OFF when installing removing the DIMM module Figure 23 Installing the DDR1 DIMM Module Both error correcting codes E...

Page 32: ...Section 2 4 Serial Port Configuration PC 2 3 1 Cable Connections Connect the serial port of the mITX GP system and the personal computer using RS 232 cable supplied with the system Then connect the AC...

Page 33: ...8 Parity none Number of Stop bits 1 Flow Control Disabled 2 5 Power Up Press the power button on the front panel Figure 25 Front Panel A few seconds after power up the U Boot prompt should be receive...

Page 34: ...leverages as much BSP elements as possible for all Freescale targets that are supported while offering the flexibility required to customize as necessary components that require platform specific mod...

Page 35: ...ment describing how to make use of LTIB to build the ISO image 3 1 Third Party Application Software Many third party applications are available for the MPC8349E mITX GP They are typically built on top...

Page 36: ...roducts are not designed intended or authorized for use as components in systems intended for surgical implant into the body or other applications intended to support or sustain life or for any other...

Reviews: