MPC8349E-mITX-GP Reference Design Platform User’s Guide, Rev. 0
22
Freescale Semiconductor
Preliminary—Subject to Change Without Notice
MPC8349E-mITX-GP Board
The RCW definitions are shown in
Figure 17
and
Figure 18
.
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
Field
LBIUCM DDRCM
—
SPMF
—
COREPLL
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
Field
—
Figure 17. Reset Configuration Word Low (RCWL) Bit Settings
0
1
2
3
4
5
6
7
8
9
10 11
12
13
14
15
Field
PCIHOST PCI64 PCI1ABR PCI2ABR COREDIS BMS BOOTSEQ SWEN
ROMLOC
—
16
17
18
19
20
21
22
23
24
25 26 27
28
29
30
31
Field
TSEC1M
TSEC2M
—
TLE LALE LDP
—
Figure 18. Reset Configuration Word High (RCWH) Bit Settings
Table 14. RCWL Bit Descriptions
Bits
Name
Meaning
Description
0
LBIUCM
Local bus memory
controller clock
mode
Local Bus Controller Clock: CSB_CLK
0: Default
ratio 1:1
1:
ratio 2:1
1
DDRCM
DDR SDRAM
memory controller
clock mode
DDR Controller Clock: CSB_CLK
0: Default
ratio 1:1
1:
ratio 2:1
2–3
—
Reserved
Must be cleared.
4–7
SPMF[0–3]
System PLL
multiplication
factor
0000
16:1
0001
Reserved
0010
2:1
0011
3:1
0100 (default)
4:1
0101
5:1