NXP Semiconductors MPC5644A, Reference Manual, Page: 849 / 1735

Enhanced Time Processing Unit (eTPU2)
MPC5644A Microcontroller Reference Manual, Rev. 6
Freescale Semiconductor 849
Output Pin Control Logic and Pin State Output Register – PSTO
The output signal control logic uses OPACA/B, the Pre-defined Channel Mode (PDCM) and the User
Defined Channel Mode (UDCM), and the microcode Pin State Control (PSC and PSCS) fields. It is
responsible for setting the Pin State Output (PSTO) register to the specified logic value required by
microcode, by input events, or by Match A and/or Match B events. The PSTO register stores the driven
pin state determined by the Pin Control logic. The Output Buffer Enable signal, if used at MCU
integration, must be set by microcode (using TBSA field) to make the pad propagate the PSTO register
output to the actual pin.
PSTO register output also goes to the microengine branch logic, enabling branching on the driven pin state
(see
Figure 24-37 ). PSTO is set to 0 on reset.
The PSC and PSCS microcode fields are used for setting the PSTO register to a fixed value, or to the value
specified by the OPACA or OPACB microcode field, as shown in
Table 24-45 .
For details refer to Section 24.5.9.3, Channel control and configuration microoperations .
On occurrence of match recognitions or transition detections, the pin control logic sets PSTO value
according to the event number (Match A/Transition A or Match B/Transition B) and the contents of
OPACA/IPACA or OPACB/IPACB registers. There are cases in which two match or transition events may
occur at the same time, each of them trying to force a different pin action. The resolution of the selected
match event which sets the value depends on the Pre-defined Channel Mode (PDCM) register and the User
Defined Channel Mode (UDCM). For details refer to
Section , Match/Transition Pin Action Conflict
Resolution .
PSTI and PSS – Pin State Input and Pin Sampled State Registers
During the time slot transition period, or whenever the CHAN register is written by microcode, the
filtered
1
input signal PSTI or output signal PSTO (selected by the ETPU_CxCR bit ETPD) is sampled into
the branch logic as the PSS flag (see Figure 24-37 and Table 24-113 ). The microcode can then branch on
either the currently driven (PSTO) or input (PSTI) pin state, or on sampled pin state (PSS, which is stable
as long as CHAN does not change).
2
On the microinstruction fields IPACA/B and OPACA/B this value is neutral, meaning that
IPAC/OPAC register values are not changed.
Table 24-45. PSC and PSCS encoding
PSC Output Pin Action
00 Force pin state according to
OPACA (PSCS = 0) or OPACB (PSCS = 1).
01 Force pin high.
10 Force pin low.
11 Do not change pin state.
1. The filter can be bypassed.