NXP Semiconductors MPC5644A, Reference Manual, Page: 642 / 1735

Configurable Enhanced Modular IO Subsystem (eMIOS200)
MPC5644A Microcontroller Reference Manual, Rev. 6
642 Freescale Semiconductor
22.3 External signals description
Each channel has one external input and one external output signal. Depending on the chip integration, the
input and output signals can be connected to two separate pins, or to a single bidirectional pin. See
Chapter 3 Signal Description for details.
22.4 Memory map/register definition
22.4.1 Memory map
The overall address map organization is shown in Table 22-2 .
NOTE
Whenever an access to either an absent register, an absent channel or a
reserved address is performed, the eMIOS200 responds by asserting a
Transfer Error signal from the slave bus (or STAC bus).
Output Pulse Width and Frequency Modulation Buffered OPWFMB on page 22-674
Output Pulse Width Modulation Buffered OPWMB on page 22-679
Table 22-2. MPC5644A eMIOS memory map
Offset from
EMIOS_BASE
(0xC3FA_0000)
Register Location
Global registers
0x0000 EMIOS_MCR — Module Configuration Register on page 22-649
0x0004 EMIOS_GFR — Global FLAG Register on page 22-651
0x0008 EMIOS_OUDR — Output Update Disable Register on page 22-651
0x000C EMIOS_UCDIS — Channel Disable Register on page 22-652
0x000C–0x001F Reserved
Channel 0 registers
0x0020 EMIOS_CADR[0] — Channel A Data Register on page 22-653
0x0024 EMIOS_CBDR[0] — Channel B Data Register on page 22-653
0x0028 EMIOS_CCNTR[0] — Channel Counter Register on page 22-654
0x002C EMIOS_CCR[0] — Channel Control Register on page 22-655
0x0030 EMIOS_CSR[0] — Channel Status Register on page 22-659
0x0034 EMIOS_ALTA[0]
1
— Alternate A Register on page 22-660
Table 22-1. All available MPC5644A eMIOS channel configurations (continued)
Description Name Location