NXP Semiconductors MPC5644A, Reference Manual, Page: 654 / 1735

Configurable Enhanced Modular IO Subsystem (eMIOS200)
MPC5644A Microcontroller Reference Manual, Rev. 6
654 Freescale Semiconductor
22.4.3.3 eMIOS200 Channel Counter Register (EMIOS_CCNTR[n])
The EMIOS_CCNTR[ n ] contains the value of the internal counter for eMIOS channel n . When GPIO
mode is selected or the channel is frozen the EMIOS_CCNTR[ n ] is read/write. For all other modes, the
EMIOS_CCNTR[ n ] is a read-only register. When entering some operation modes, this register is
automatically cleared (refer to Section 22.5.1.1, Channel modes of operation , for details).
Depending on its configuration, a channel may have an internal counter or not. If at least one mode that
requires the counter is implemented, the counter is present, otherwise it is not.
SAIC
1
— A2 B2 B2 — —
SAOC
1
A2 A1 B2 B2 — —
IPWM — A2 — B1 — —
IPM — A2 — B1 — —
DAOC A2 A1 B2 B1 — —
MCB
1
A2 A1 B2 B2 — —
OPWFMB A2 A1 B2 B1 — —
OPWMB A2 A1 B2 B1 — —
1
In this mode, the register EMIOS_CBDR[n] is not used but B2 can be accessed.
Offset: UC[ n ] base a 0x0008 Access: User read/write
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
R 0 0 0 0 0 0 0 0 C[0:23]
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
R C[0:23]
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
1
In GPIO mode or freeze action, this register is writable.
Figure 22-8. eMIOS200 Channel Counter Register (EMIOS_CCNTR[n])
Table 22-7. EMIOS_CADR[n], EMIOS_CBDR[n], and EMIOS_ALTA[n] values assignment (continued)