NXP Semiconductors MPC5644A, Reference Manual, Page: 660 / 1735

Configurable Enhanced Modular IO Subsystem (eMIOS200)
MPC5644A Microcontroller Reference Manual, Rev. 6
660 Freescale Semiconductor
22.4.3.6 eMIOS200 UC Alternate A Register (EMIOS_ALTA[n])
The EMIOS_ALTA[ n ] register provides an alternate read-only address to access A2 channel registers in
GPIO, PEC, WPTA, and OPWMT modes. If the EMIOS_CADR[ n ] is used with EMIOS_ALTA[ n ], both
A1 and A2 registers can be accessed in these modes.
22.5 Functional description
The eMIOS200 provides independently operating channels that can be configured and accessed by a host
MCU. The channels are reduced-function versions of Unified Channels. The four time bases can be shared
by the channels through four counter buses and each channel can generate its own time base.
The eMIOS200 block is reset asynchronously. All registers are cleared on reset.
22.5.1 Unified channel (UC)
Figure 22-12 shows the eMIOS200 Unified Channel
1
block diagram. Each Unified Channel consists of:
• Counter bus selector, which selects the time base to be used by the channel for all timing functions
UCOUT Unified Channel Output
The UCOUT bit reflects the output pin state.
FLAG FLAG
The FLAG bit is set when an input capture or a match event in the comparators occurred. This bit
must be cleared by software writing a ‘1’.
0 FLAG cleared.
1 FLAG set event has occurred.
Note: When the DMA bit is set, the FLAG bit can be cleared by the DMA controller.
Address: UC[ n ] base a 0x0014 Access: User read/write
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
R 0 0 0 0 0 0 0 0 ALTA[0:23]
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
R ALTA[0:23]
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Figure 22-11. eMIOS200 UC Alternate A Register (EMIOS_ALTA[n])
1. The eMIOS200 Unified Channel has a reduced set of functions when compared to MPC5500 Unified Channel
implementations.
Table 22-10. EMIOS_CSR[n] field description (continued)
Field Description