NXP Semiconductors MPC5644A, Reference Manual, Page: 1350 / 1735

Enhanced Serial Communication Interface (ESCI)
MPC5644A Microcontroller Reference Manual, Rev. 6
1350 Freescale Semiconductor
31.3.2.7 LIN Control Register 1 (eSCI_LCR1)
This register provides control bits to control and configure the LIN hardware. This register provides the
interrupt enable bits for the interrupt flags in
Interrupt Flag and Status Register 2 (eSCI_IFSR2) .
eSC 0x000C Write: Anytime
R
LRES
0
WUD
0 0
PRTY LIN RXIE TXIE WUIE STIE PBIE CIE CKIE FCIE
W WU
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Figure 31-8. LIN Control Register 1 (eSCI_LCR1)
Table 31-12. eSCI_LCR1 Field Descriptions
Field Description
LRES LIN Protocol Engine Stop and Reset. This bit is used to stop and reset the LIN protocol engine as
described in
Section 31.4.6.7, LIN protocol engine stop and reset ”.
0 LIN protocol engine is operational.
1 LIN protocol engine is reset and stopped.
WU LIN Bus Wake-Up Trigger. This bit is used to trigger the generation of a wake-up signal frame on the
LIN bus, as described in
Section 31.4.6.6, LIN wake up ”.
0 Write has no effect.
1 Write triggers the generation of a wake-up signal.
WUD LIN Bus Wake-Up Delimiter Time. This field determines how long the LIN protocol engine waits after
the end of the transmitted wake-up signal, before starting the next LIN frame transmission.
00 3 bit times.
01 7 bit times.
10 31 bit times.
11 63 bit times.
PRTY Parity Generation Control. This bit controls the generation of the two parity bits in the LIN header.
0 Parity bits generation disabled.
1 Parity bits generation enabled.
LIN LIN Mode Control. This bit controls whether the device is in SCI or LIN Mode.
0 SCI Mode.
1 LIN Mode.
RXIE Receive Data Ready Interrupt Enable. This bit controls the eSCI_IFSR2[RXRDY] interrupt request
generation.
0 RXRDY interrupt request generation disabled.
1 RXRDY interrupt request generation enabled.
TXIE Transmit Data Ready Interrupt Enable. This bit controls the eSCI_IFSR2[TXRDY] interrupt request
generation.
0 TXRDY interrupt request generation disabled.
1 TXRDY interrupt request generation enabled.
WUIE LIN Wake-up Received Interrupt Enable. This bit controls the eSCI_IFSR2[LWAKE] interrupt request
generation.
0 LWAKE interrupt request generation disabled.
1 LWAKE interrupt request generation enabled.