NXP Semiconductors MPC5644A, Reference Manual, Page: 1385 / 1735

Enhanced Serial Communication Interface (ESCI)
MPC5644A Microcontroller Reference Manual, Rev. 6
Freescale Semiconductor 1385
31.4.6.6.1 LIN Wake-Up Request Generation
The eSCI module can cause the LIN bus to exit the sleep mode by sending a wake-up signal frame, which
consists of a wake-up signal 0x80 (consisting of 8 dominant bits followed by 1 recessive bit), followed by
the wake-up delimiter period as defined by the WUD field in the
LIN Control Register 1 (eSCI_LCR1) .
Figure 31-42. LIN Wake-Up Signal Frame
The application triggers the transmission of a wake-up signal frame by writing 1 to the LIN bus wake-up
trigger WU in the
LIN Control Register 1 (eSCI_LCR1) .
The LIN Specification 2.0 requires the generation of LIN wake-up signals as dominant pulses longer than
250

s and shorter than 5 ms. To achieve this, the eSCI module has to programmed to a baud rate between
32 kBaud and 1.6 kBaud. With each of these baud rate settings, the wake-up signal is transmitted as a
dominant pulse longer than 250

s and shorter than 5 ms.
31.4.6.6.2 LIN wake-up request detection
The eSCI module detects a LIN wake-up requests when
e) one of the characters 0x00, 0x80, or 0xC0 has been received,
f) followed by zero or more low bits,
g) followed by at least one high bit, and
h) no LIN frame transmission or reception is started or running during the reception above
If a LIN wake-up request has been detected, the LIN wake-up flag LWAKE in the Interrupt Flag and Status
Register 2 (eSCI_IFSR2) will be set after the reception of the first high bit.
The LIN Specification 2.0 requires the detection of LIN wake-up requests as dominant pulses longer than
150

s. To achieve this, the eSCI module has to programmed to the maximum baud rate that is not greater
than 43.77 kBaud. With this baud rate setting, any dominant pulse longer than 150

s is decoded as at least
7 dominant bits (one start and 6 data bits) and consequently as one of the characters 0xC0, 0x80, or 0x00.
31.4.6.7 LIN protocol engine stop and reset
The LIN protocol engine is stopped and reset when the application set the LRES control bit in the LIN
Control Register 1 (eSCI_LCR1) to 1. In this case, the LIN protocol engine will stop immediately. No new
transmissions or receptions are initiated, the LIN serial bus is driven with the recessive value 1.
Additionally to the stop and reset of the LIN protocol engine the receiver and transmitter modules are
stopped and reset as well, and the receive and transmit DMA requests are deasserted.
In order to start the LIN Protocol Engine with idle transmitter and receiver processes, the LRES bit should
be asserted until all of the status bits DACT, LACT, TACT, and RACT in the
Interrupt Flag and Status
BIT0
START
BIT
BIT1 BIT2 BIT3 BIT4 BIT5 BIT6 BIT7
BREAK
Wake-Up Signal Wake-Up Delimiter
LIN Frame Wake-Up Signal Frame