NXP Semiconductors MPC5605BK, Reference Manual

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Chapter 20 System Integration Unit Lite (SIUL)
MPC5606BK Microcontroller Reference Manual, Rev. 2
Freescale Semiconductor 351
20.5 Memory map and register description
This section provides a detailed description of all registers accessible in the SIUL module.
20.5.1 SIUL memory map
Table 20-2 gives an overview of the SIUL registers implemented.
Table 20-2. SIUL memory map
Base address: 0xC3F9_0000
Address offset Register Location
0x0000 Reserved
0x0004 MCU ID Register #1 (MIDR1) on page 353
0x0008 MCU ID Register #2 (MIDR2) on page 354
0x000C–0x0013 Reserved
0x0014 Interrupt Status Flag Register (ISR) on page 355
0x0018 Interrupt Request Enable Register (IRER) on page 356
0x001C–0x00 Reserved
0x0028 Interrupt Rising-Edge Event Enable Register (IREER) on page 356
0x002C Interrupt Falling-Edge Event Enable Register (IFEER) on page 357
0x0030 Interrupt Filter Enable Register (IFER) on page 358
0x0034–0x003F Reserved
0x0040–0x0168 Pad Configuration Registers (PCR0–PCR148)
1
on page 359
0x016A–0x04FF Reserved
0x0500–0x053C Pad Selection for Multiplexed Inputs Registers
(PSMI0_3–PSMI60_63) on page 361
0x0540–0x05FF Reserved
0x0600–0x06A0 GPIO Pad Data Output Registers (GPDO0_3–GPDO148_151)
2
on page 366
0x06A4–0x07FF Reserved
0x0800–0x08A0 GPIO Pad Data Input Registers (GPDI0_3–GPDI148_151)
3
on page 367
0x08A4–0x0BFF Reserved
0x0C00–0x0C10 Parallel GPIO Pad Data Out Registers (PGPDO0 – PGPDO4) on page 367
0x0C14–0x0C3F Reserved
0x0C40–0x0C50 Parallel GPIO Pad Data In Registers (PGPDI0 – PGPDI4) on page 368
0x0C54–0x0C7F Reserved
0x0C80–0x0CA4 Masked Parallel GPIO Pad Data Out Register
(MPGPDO0–MPGPDO9) on page 369
0x0CA8–0x0FFF Reserved