NXP Semiconductors MKW01Z128, Reference Manual

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33.3.3 UART Control Register 1 (UARTx_C1)
This read/write register controls various optional features of the UART system.
Address: Base a 2h offset
Bit 7 6 5 4 3 2 1 0
Read
LOOPS UARTSWAI RSRC M WAKE ILT PE PT
Write
Reset 0 0 0 0 0 0 0 0
UARTx_C1 field descriptions
Field Description
7
LOOPS
Loop Mode Select
Selects between loop mode and normal 2-pin full-duplex modes. When LOOPS is set, the transmitter
output is internally connected to the receiver input.
0 Normal operation - RxD and TxD use separate pins.
1 Loop mode or single-wire mode where transmitter outputs are internally connected to receiver input.
(See RSRC bit.) RxD pin is not used by UART.
6
UARTSWAI
UART Stops in Wait Mode
0 UART clocks continue to run in Wait mode so the UART can be the source of an interrupt that wakes
up the CPU.
1 UART clocks freeze while CPU is in Wait mode.
5
RSRC
Receiver Source Select
This field has no meaning or effect unless LOOPS is set to 1. When LOOPS is set, the receiver input is
internally connected to the TxD pin and RSRC determines whether this connection is also connected to
the transmitter output.
0 Provided LOOPS is set, RSRC is cleared, selects internal loop back mode and the UART does not
use the RxD pins.
1 Single-wire UART mode where the TxD pin is connected to the transmitter output and receiver input.
4
M
9-Bit or 8-Bit Mode Select
This field configures the UART to be operated in 9-bit or 8-bit data mode.
0 Normal - start + 8 data bits (lsb first) + stop.
1 Receiver and transmitter use 9-bit data characters start + 8 data bits (lsb first) + 9th data bit + stop.
3
WAKE
Receiver Wakeup Method Select
This field selects the receiver wakeup method.
0 Idle-line wake-up.
1 Address-mark wake-up.
2
ILT
Idle Line Type Select
Table continues on the next page...
Chapter 33 Universal asynchronous receiver/transmitter (UART1 and UART2)
MKW01Z128 MCU Reference Manual, Rev. 3, 04/2016
Freescale Semiconductor, Inc. 651