NXP Semiconductors MKW01Z128, Reference Manual, Page: 783 / 884

UARTx_C1 field descriptions (continued)
Field Description
Setting this field to 1 ensures that the stop bits and logic 1 bits at the end of a character do not count
toward the 10 or 11 bit times of logic high level needed by the idle line detection logic.
0 Idle character bit count starts after start bit.
1 Idle character bit count starts after stop bit.
1
PE
Parity Enable
Enables hardware parity generation and checking. When parity is enabled, the most significant bit (msb) of
the data character, eighth or ninth data bit, is treated as the parity bit.
0 No hardware parity generation or checking.
1 Parity enabled.
0
PT
Parity Type
Provided parity is enabled (PE = 1), this field selects even or odd parity. Odd parity means the total
number of 1s in the data character, including the parity bit, is odd. Even parity means the total number of
1s in the data character, including the parity bit, is even.
0 Even parity.
1 Odd parity.
33.3.4 UART Control Register 2 (UARTx_C2)
This register can be read or written at any time.
Address: Base a 3h offset
Bit 7 6 5 4 3 2 1 0
Read
TIE TCIE RIE ILIE TE RE RWU SBK
Write
Reset
0 0 0 0 0 0 0 0
UARTx_C2 field descriptions
Field Description
7
TIE
Transmit Interrupt Enable for TDRE
0 Hardware interrupts from TDRE disabled; use polling.
1 Hardware interrupt requested when TDRE flag is 1.
6
TCIE
Transmission Complete Interrupt Enable for TC
0 Hardware interrupts from TC disabled; use polling.
1 Hardware interrupt requested when TC flag is 1.
5
RIE
Receiver Interrupt Enable for RDRF
0 Hardware interrupts from S1[RDRF] disabled; use polling.
1 Hardware interrupt requested when S1[RDRF] flag is 1.
4
ILIE
Idle Line Interrupt Enable for IDLE
Table continues on the next page...
Register definition
MKW01Z128 MCU Reference Manual, Rev. 3, 04/2016
652 Freescale Semiconductor, Inc.