NXP Semiconductors MC9S12VRP64, Owner Reference Manual

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Device Overview S12VRP-Series
MC9S12VRP Family Reference Manual Rev. 1.3
NXP Semiconductors 29
1.7.1 Part ID Assignments
The part ID is located in two 8-bit registers PARTIDH and PARTIDL (addresses 0x001A and 0x001B).
The read-only value is a unique part ID for each revision of the chip.
Table 1-5 shows the assigned part ID
number and mask set number.
1.8 Signal Description and Device Pinouts
This section describes signals that connect off-chip. It includes a pinout diagram, a table of signal
properties, and detailed discussion of signals. It is built from the signal description sections of the
individual IP blocks on the device.
1.8.1 Pin Assignment Overview
Table 1-6 provides a summary of which ports are available for the 48-pin package option.
NOTE
To avoid current drawn from floating inputs, all non-bonded pins should be
configured as output or configured as input with a pull up or pull down
device enabled
1.8.2 Detailed Signal Descriptions
This section describes the signal properties.
Table 1-5. Assigned Part ID Numbers
Device Mask Set Number Part ID
S12VRP48 0N80T $3A80
S12VRP64 0N80T $3A80
Table 1-6. Port Availability by Package Option
Port 48 LQFP
Port AD PAD[5:0]
Port E PE[1:0]
Port P PP[5:0]
Port S PS[3:0]
Port T PT[3:0]
Port L PL[5:0]
Sum of ports 28
I/O power pairs VDDX/VSSX 2/2