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MC9S12VRP Family Reference Manual Rev. 1.3

NXP Semiconductors

169

Chapter 5

Background Debug Module (S12SBDMV1)

Table 5-1. Revision History

5.1

Introduction

This section describes the functionality of the background debug module (BDM) sub-block of the HCS12S
core platform.

The background debug module (BDM) sub-block is a single-wire, background debug system implemented
in on-chip hardware for minimal CPU intervention. All interfacing with the BDM is done via the BKGD
pin.

The BDM has enhanced capability for maintaining synchronization between the target and host while
allowing more flexibility in clock rates. This includes a sync signal to determine the communication rate
and a handshake signal to indicate when an operation is complete. The system is backwards compatible to
the BDM of the S12 family with the following exceptions:

•

TAGGO command not supported by S12SBDM

•

External instruction tagging feature is part of the DBG module

•

S12SBDM register map and register content modified

•

Family ID readable from BDM ROM at global address 0x3_FF0F in active BDM
(value for devices with HCS12S core is 0xC2)

•

Clock switch removed from BDM (CLKSW bit removed from BDMSTS register)

5.1.1

Features

The BDM includes these distinctive features:

•

Single-wire communication with host development system

•

Enhanced capability for allowing more flexibility in clock rates

•

SYNC command to determine communication rate

•

GO_UNTIL command

Revision Number

Date

Sections

Affected

Summary of Changes

1.05

07.Dec.2010

Standardized format of revision history table header.

1.06

02.Mar.2011

Corrected BPAE bit description.
Removed references to fixed VCO frequencies

1.07

27.Sep.2012

General

Changed references to device level.

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Summary of Contents for MC9S12VRP64

Page 1: ...S12 MagniV Microcontrollers nxp com MC9S12VRP Series Reference Manual and Datasheet MC9S12VRP64 Rev 1 3 19 Sep 2017 ...

Page 2: ...n Description 01 MAR 2017 1 0 Updated Data Flash size for S12VRP48 option Table 1 2 Removed internal register bit reference 13 3 4 13 376 Updated NVM timing for Erase D Flash Sector Table I 1 Removed Preliminary marking 7 AUG 2017 1 1A Minor corrections in Chapter 1 Device Overview S12VRP Series Chapter 2 Port Integration Module S12VRPPIMV1 and Chapter 14 Low Side Driver LS2DRV S12LS2DRV_V1 Update...

Page 3: ... Communication Interface Module SCI 22 1 5 13 Analog to Digital Converter Module ADC 23 1 5 14 Supply Voltage Sense BATS 23 1 5 15 On Chip Voltage Regulator system VREG 23 1 5 16 Low side driver LSDRV 24 1 5 17 Low side driver LS2DRV 24 1 5 18 Current Sense Amplifier 24 1 5 19 High side drivers HSDRV 24 1 5 20 Background Debug BDM 24 1 5 21 Debugger DBG 25 1 6 Block Diagram 25 1 7 Family Memory Ma...

Page 4: ...cific PIM Registers 61 2 3 3 PIM Generic Registers 68 2 3 4 PIM Generic Register Exceptions 74 2 4 Functional Description 82 2 4 1 General 82 2 4 2 Registers 83 2 4 3 Pin I O Control 83 2 4 4 Pull Devices 85 2 4 5 Increased Drive Strength on PP2 PP1 and PP0 85 2 4 6 High Side Drivers and Low Side Drivers 85 2 4 7 Interrupts 85 2 4 8 High Voltage Input 87 2 5 Initialization and Application Informat...

Page 5: ...Pad Supply Pins 115 4 2 6 VSS Ground Pin 116 4 2 7 API_EXTCLK API external clock output pin 116 4 2 8 VDD Internal Regulator Output Supply Core Logic 116 4 2 9 VDDF Internal Regulator Output Supply NVM Logic 116 4 2 10 TEMPSENSE Internal Temperature Sensor Output Voltage 116 4 3 Memory Map and Registers 117 4 3 1 Module Memory Map 117 4 3 2 Register Descriptions 119 4 4 Functional Description 153 ...

Page 6: ... 1 Security 176 5 4 2 Enabling and Activating BDM 176 5 4 3 BDM Hardware Commands 177 5 4 4 Standard BDM Firmware Commands 178 5 4 5 BDM Command Structure 179 5 4 6 BDM Serial Interface 181 5 4 7 Serial Interface Hardware Handshake Protocol 184 5 4 8 Hardware Handshake Abort Procedure 186 5 4 9 SYNC Request Timed Reference Pulse 189 5 4 10 Instruction Tracing 189 5 4 11 Serial Communication Time O...

Page 7: ...r 7 Interrupt Module S12SINTV1 7 1 Introduction 237 7 1 1 Glossary 237 7 1 2 Features 237 7 1 3 Modes of Operation 238 7 1 4 Block Diagram 238 7 2 External Signal Description 239 7 3 Memory Map and Register Definition 239 7 3 1 Register Descriptions 239 7 4 Functional Description 240 7 4 1 S12S Exception Requests 240 7 4 2 Interrupt Prioritization 240 7 4 3 Reset Exception Requests 241 7 4 4 Excep...

Page 8: ...escription 272 9 2 1 PWM7 PWM0 PWM Channel 7 0 273 9 3 Memory Map and Register Definition 273 9 3 1 Module Memory Map 273 9 3 2 Register Descriptions 273 9 4 Functional Description 287 9 4 1 PWM Clock Select 287 9 4 2 PWM Channel Timers 291 9 5 Resets 299 9 6 Interrupts 300 Chapter 10 Serial Communication Interface S12SCIV6 10 1 Introduction 301 10 1 1 Glossary 301 10 1 2 Features 302 10 1 3 Modes...

Page 9: ... Block Diagrams 342 11 2 External Signal Description 342 11 2 1 IOC1 IOC0 Input Capture and Output Compare Channel 1 0 342 11 3 Memory Map and Register Definition 343 11 3 1 Module Memory Map 343 11 3 2 Register Descriptions 343 11 4 Functional Description 354 11 4 1 Prescaler 355 11 4 2 Input Capture 356 11 4 3 Output Compare 356 11 5 Resets 357 11 6 Interrupts 357 11 6 1 Channel 1 0 Interrupt C ...

Page 10: ...Introduction 371 13 1 1 Features 371 13 1 2 Modes of Operation 372 13 1 3 Block Diagram 372 13 2 External Signal Description 373 13 2 1 LS0 LS1 Low Side Driver Pins 373 13 2 2 LSGND Low Side Driver Ground Pin 373 13 3 Memory Map and Register Definition 373 13 3 1 Module Memory Map 373 13 3 2 Register Definition 375 13 3 3 Port LS Data Register LSDR 375 13 3 4 LSDRV Configuration Register LSCR 376 ...

Page 11: ...Chapter 15 Current Sense Amplifier Module ISENSEV1 15 1 Features 393 15 2 Modes of Operation 393 15 3 Block Diagram 394 15 4 External Signal Description 394 15 4 1 AMPP Current Sense Amplifier Non Inverting Input Pin 394 15 4 2 AMPM Current Sense Amplifier Inverting Input Pin 394 15 4 3 AMP Current Sense Amplifier Output Pin 394 15 5 Memory Map and Register Definition 395 15 5 1 Register Summary 3...

Page 12: ...ion 425 17 1 3 Block Diagram 426 17 2 External Signal Description 426 17 2 1 VSENSE Supply Battery Voltage Sense Pin 426 17 2 2 VSUP Voltage Supply Pin 427 17 3 Memory Map and Register Definition 427 17 3 1 Register Summary 427 17 3 2 Register Descriptions 428 17 4 Functional Description 433 17 4 1 General 433 17 4 2 Interrupts 434 Chapter 18 64 KByte Flash Module S12FTMRG64K4KV2 18 1 Introduction...

Page 13: ...mum Ratings 491 A 1 5 ESD Protection and Latch up Immunity 492 A 1 6 Recommended Capacitor 494 A 1 7 Operating Conditions 494 A 1 8 Power Dissipation and Thermal Characteristics 495 A 2 General Purpose I O Characteristics 497 A 2 1 High Voltage Inputs HVI Characteristics 500 A 3 Supply Currents 500 A 3 1 Measurement Conditions 500 Appendix B CPMU Electrical Specifications VREG OSC IRC PLL B 1 VREG...

Page 14: ...Characteristics 521 Appendix G ISENSE Electrical Specifications G 1 Operating Characteristics 522 Appendix H BATS Electrical Specifications H 1 Static Electrical Characteristics 523 H 2 Dynamic Electrical Characteristics 524 Appendix I NVM Electrical Parameters I 1 NVM Timing Parameters 525 I 2 NVM Reliability Parameters 527 Appendix J Package Information Appendix K Ordering Information Appendix L...

Page 15: ...4 0x00A0 0x00C7 Pulse Width Modulator 6 Channels PWM Map 542 L 15 0x00C8 0x00CF Serial Communication Interface SCI0 Map 543 L 16 0x00D0 0x00D7 Serial Communication Interface SCI1 Map 545 L 17 0x0100 0x0113 NVM Control Register FTMRG Map 545 L 18 0x0120 Interrupt Vector Base Register 546 L 19 0x0140 0x0147 High Side Drivers HSDRV2C 547 L 20 0x0150 0x0157 Low Side Drivers LSDRV 547 L 21 0x0158 0x015...

Page 16: ...MC9S12VRP Family Reference Manual Rev 1 3 16 NXP Semiconductors ...

Page 17: ... the integration of several key system components into a single device optimizing system architecture and achieving significant space savings The S12VRP Series delivers all the advantages and efficiencies of a 16 bit MCU while retaining the low cost power consumption EMC and code size efficiency advantages currently enjoyed by users of NXP s existing 8 bit and 16 bit MCU families The S12VRP Series...

Page 18: ...ies differences are outlined in AN5328 also including a comparison to MM912_634 Table 1 2 S12VRP Series Feature S12VRP48 S12VRP64 Package option 48LQFP Core HCS12 Bus frequency 25 MHz Flash memory ECC 48 KB 64 KB Data Flash 2 KB 4 KB RAM 6 KB LIN Physical layer 1 SCI 1 2 Timer TIM0 TIM1 2ch x16 bit 2ch x16 bit PWM 8ch x 8 bit or 4ch x 16 bit 10 bit ADC channels 122 Frequency modulated PLL Yes Inte...

Page 19: ...nels mapped to HVI pins One serial communication interface SCI module supporting LIN communications with RX connected to a timer channel for internal oscillator calibration purposes if desired One on chip LIN physical layer transceiver fully compliant with the LIN 2 2A SAE J2602 2 standards routed to the SCI module supporting LIN communications One additional SCI not connected to LIN physical laye...

Page 20: ...yte counts including many single byte instructions This allows much more efficient use of ROM space Extensive set of indexed addressing capabilities including Using the stack pointer as an indexing register in all indexed operations Using the program counter as an indexing register in all but auto increment decrement mode Accumulator offsets using A B or D accumulators Automatic index predecrement...

Page 21: ...red with GPIO functionality 1 5 5 Internal RC Oscillator IRC Factory trimmed internal reference clock 1 MHz internal RC oscillator with 1 3 accuracy over rated temperature range 1 5 6 Internal Phase Locked Loop IPLL Phase locked loop clock frequency multiplier No external components required Reference divider and multiplier allow large variety of clock rates Automatic bandwidth control mode for lo...

Page 22: ...ion Programmable period and duty cycle per channel Center aligned or left aligned outputs Programmable clock select logic with a wide range of frequencies 1 5 11 LIN physical layer transceiver LINPHY Compliant with LIN Physical Layer 2 2A specification Compliant with the SAE J2602 2 LIN standard Standby mode with glitch filtered wake up Slew rate selection optimized for the baud rates 10 4kBit s 2...

Page 23: ... in stop modes Continuous conversion mode Multiple channel scans GPIO pins can also be used as digital I O HVI pins can also be used as high voltage inputs Pins can be used as keyboard wake up interrupt KWI Internal voltages monitored with the ADC module VSUP or VSENSE Chip temperature sensor VHT or band gap voltage VBG VRH VRL VRH VRL 2 VDDF 1 5 14 Supply Voltage Sense BATS VSENSE VSUP pin low or...

Page 24: ... side driver LS2DRV Additional low side driver targeted for up to 20mA current capability Internal Timer or PWM channels can be routed to control the low side driver Over current protection with shutdown and interrupt 1 5 18 Current Sense Amplifier One channel integrated op amp functionality 1 5 19 High side drivers HSDRV Two high side drivers targeted for up to 50mA current capability Internal Ti...

Page 25: ...h Modulator PWM 64 or 48 KB Program Flash with ECC CPU12 V1 COP Watchdog PLL with Frequency Modulation option Debug Module 3 comparators 64 Byte Trace Buffer Reset Generation and Test Entry RXD TXD Auton Periodic Int PT3 PT0 PT1 PT2 PTT PP0 PGPIO PP1 PP2 EVDD PTP IOC1_1 IOC0_0 IOC0_1 IOC1_0 VDDX1 VSSX1 VDDX2 VSSX2 HS0 HS1 5V IO Supply Output VSS Low Power Pierce Oscillator SCI0 Asynchronous Serial...

Page 26: ...ower management 12 0x0040 0x006F TIM0 timer module 8 channels 48 0x0070 0x009F ADC analog to digital converter 16 channels 48 0x00A0 0x00C7 PWM pulse width modulator 8 channels 40 0x00C8 0x00CF SCI0 serial communication interface 8 0x00D0 0x00D7 SCI1 serial communication interface 8 0x00D8 0x00FF Reserved 40 0x0100 0x0113 FTMRG control registers 20 0x0114 0x011F Reserved 12 0x0120 INT interrupt mo...

Page 27: ...256K global memory space is visible through the P Flash window located in the 64k local memory map located at 0x8000 0xBFFF using the PPAGE register NOTE Flash space on page 0xC in Figure 1 2 is not available on S12VRP48 0x0280 0x02EF Reserved 112 0x02F0 0x02FF CPMU clock and power management 16 0x0300 0x03FF Reserved 256 Table 1 4 S12VRP Series Memory Address Ranges Device Memory Size Address S12...

Page 28: ...Window RAM RAM Unimplemented Unimplemented Register Space Register Space Internal NVM Resources Internal NVM Resources P Flash Space P Flash Space P Flash Space P Flash Space EEPROM Data Flash EEPROM Data Flash Register Space Register Space Page 0xE Page 0xE Page 0xF Page 0xF Page 0xD Page 0xD Page 0xC Page 0xC NVMRES 1 0x3_0000 0x3_4000 0x3_8000 RAM RAM Unimplemented Unimplemented 0x1400 0x2800 P...

Page 29: ...uilt from the signal description sections of the individual IP blocks on the device 1 8 1 Pin Assignment Overview Table 1 6 provides a summary of which ports are available for the 48 pin package option NOTE To avoid current drawn from floating inputs all non bonded pins should be configured as output or configured as input with a pull up or pull down device enabled 1 8 2 Detailed Signal Descriptio...

Page 30: ... wake up capability KWAD 5 0 These signals can have a pull up or pull down device selected and enabled on a per signal basis Out of reset the pull devices are disabled 1 8 2 5 PE 1 0 Port E I O Signals PE 1 0 are general purpose input or output signals The signals each have pull down device enabled by a single control bit for this signal group Out of reset the pull down devices are enabled 1 8 2 6...

Page 31: ...n be connected to the supply Battery line for voltage measurements The voltage present at this input is scaled down by an internal voltage divider and can be routed to the internal ADC via an analog multiplexer The pin itself is protected against reverse battery connections To protect the pin from external fast transients an external resistor is needed 1 8 2 15 AN 11 0 ADC Input Signals AN 11 0 ar...

Page 32: ...s clock ECLK NOTE This feature is only intended for debug purposes at room temperature It must not be used for clocking external devices in an application 1 8 2 21 ETRIG 1 0 These signals are inputs to the Analog to Digital Converter Their purpose is to trigger ADC conversions 1 8 2 22 IOC0_ 1 0 Signals The signals IOC0_ 1 0 are associated with the input capture or output compare functionality of ...

Page 33: ...SA 1 8 3 3 VSS Core Ground Pin The voltage supply of nominally 1 8V is generated by the internal voltage regulator The return current path is through the VSS pin 1 8 3 4 LGND LINPHY Ground Pin LGND is the ground pin for the LIN physical layer LINPHY 1 8 3 5 LSGND Ground Pin for Low Side Drivers LSGND is the shared ground pin for the low side drivers 1 8 3 6 VSUP Voltage Supply Pin for Voltage Regu...

Page 34: ...ing options VSSX2 0V Ground pin for I O drivers VDDA 5 0 V External power supply for the analog to digital converter and for the reference circuit of the internal voltage regulator VSSA 0V Ground pin for VDDA analog supply LGND 0V Ground pin for LIN physical LSGND 0V Ground pin for low side driver VSUP 12V 18V External power supply for voltage regulator and high side driver supply Mnemonic Nominal...

Page 35: ...10 PL3 HVI3 KWL3 AN9 PL2 HVI2 KWL2 AN8 PL1 HVI1 KWL1 AN7 PL0 HVI0 KWL0 AN6 VSENSE HS1 VSSX2 HS0 VSUP TEST RESET PWM3 KWP3 PP3 PWM4 ETRIG0 KWP4 PP4 PWM5 ETRIG1 IRQ KWP5 PP5 VSS EXTAL PE0 XTAL PE1 VDDX2 PGPIO PWM0 KWP0 PP0 XIRQ PWM1 KWP1 PP1 EVDD PWM2 KWP2 PP2 LGND LIN LS0 LSGND LS1 LS2 VSSX1 VDDX1 RXD1 RXD0 PS0 TXD1 LPDR1 TXD0 PS1 RXD1 PWM4 ETRIG0 PS2 MODC BKGD PS3 ECLK TXD1 PWM5 ETRIG1 PT3 IOC1_1 ...

Page 36: ... LSGND 5 LS1 OC0_1 PWM7 6 LS2 OC1_1 PWM2 7 VSSX1 8 VDDX1 VDDX 9 PS0 RXD0 RXD1 VDDX PERS PPSS Up 10 PS1 TXD0 LPDR1 TXD1 VDDX PERS PPSS Up 11 PS2 ETRIG0 PWM4 RXD1 VDDX PERS PPSS Up 12 BKGD MODC VDDX PUCR BKPUE Up 13 TEST N A TEST pin Down 14 RESET VDDX RESET pin Up 15 PP3 KWP3 PWM3 VDDX PERP PPSP Off 16 PP4 KWP4 ETRIG0 PWM4 VDDX PERP PPSP Off 17 PP5 KWP5 ETRIG1 PWM5 IRQ VDDX PERP PPSP Off 18 VSS 19 ...

Page 37: ...DX 32 PL2 HVI2 KWL2 AN8 VDDX 33 PL3 HVI3 KWL3 AN9 VDDX 34 PL4 HVI4 KWL4 AN10 VDDX 35 PL5 HVI5 KWL5 AN11 VDDX 36 PAD5 KWAD5 AN5 VDDA PER1AD PPS1AD Off 37 VSSA 38 VDDA 39 PAD4 KWAD4 AN4 VDDA PER1AD PPS1AD Off 40 PAD3 KWAD3 AN3 VDDA PER1AD PPS1AD Off 41 PAD2 KWAD2 AN2 AMPP0 VDDA PER1AD PPS1AD Off 42 PAD1 KWAD1 AN1 AMPM0 VDDA PER1AD PPS1AD Off 43 PAD0 KWAD0 AN0 AMP0 VDDA PER1AD PPS1AD Off 44 PT0 IOC0_...

Page 38: ...PPST Off 46 PT2 IOC1_0 LPRXD API_EX TCLK VDDX PERT PPST Off 47 PT3 IOC1_1 LPTXD VDDX PERT PPST Off 48 PS3 ETRIG1 PWM5 TXD1 ECLK VDDX PERS PPSS Up 1 PGPIO is EVDD type capable of driving up to 20KHz into logic level FET Package Function Power Supply Internal Pull Resistor 48 LQFP Pin 1st Func 2nd Func 3rd Func 4th Func CTRL Reset State ...

Page 39: ... Normal Single Chip Mode This mode is intended for normal device operation The opcode from the on chip memory is being executed after reset requires the reset vector to be programmed correctly The processor program is executed from internal memory 1 9 1 2 Special Single Chip Mode This mode is used for debugging single chip operation boot strapping or security related operations The background debu...

Page 40: ...erting XIRQ IRQ LIN physical layer activity SCI0 RXEDGIF or key wake up incl HVI can wake the device if enabled Static power mode Stop The oscillator is stopped in this mode By default all clocks are switched off and all counters and dividers remain frozen The autonomous periodic interrupt API COP if clocked from API clock source and enabled XIRQ IRQ key wake up incl HVI and the LIN physical layer...

Page 41: ... Unimplemented instruction trap None None Vector base F6 SWI None None Vector base F4 XIRQ X Bit None Yes Yes Vector base F2 IRQ I bit IRQCR IRQEN Yes Yes Vector base F0 RTI time out interrupt I bit CPMUINT RTIE see Section 4 1 2 3 Stop Mode Yes Vector base EE TIM0 timer channel 0 I bit TIM0TIE C0I No Yes Vector base EC TIM0 timer channel 1 I bit TIM0TIE C1I No Yes Vector base EA TIM1 timer channe...

Page 42: ...pt I bit HSIE HSOCIE No Yes Vector base AC LSDRV over current interrupt I bit LSIE LSOCIE No Yes Vector base AA LINPHY over current interrupt or TXD dominant timeout interrupt I bit LPIE LPDTIE LPOCIE No Yes Vector base A8 BATS low high battery voltage interrupt I bit BATIE BVHIE BVLIE No Yes Vector base A6 LS2DRV over current interrupt I bit LS2IE LS2OCIE No Yes Vector base A4 Reserved Vector bas...

Page 43: ... state of the word being programmed or the sector block being erased is not guaranteed 1 11 3 3 I O Pins Refer to the PIM section for reset configurations of all peripheral module ports 1 11 3 4 RAM The RAM arrays are not initialized out of reset 1 12 Module Device level Dependencies 1 12 1 ADC External Trigger Input Connection The ADC module includes external trigger inputs ETRIG0 ETRIG1 ETRIG2 a...

Page 44: ... 2 15 Autonomous Periodical Interrupt Control Register CPMUAPICTL is available on PT2 1 12 5 COP Configuration The COP time out rate bits CR 2 0 and the WCOP bit in the CPMUCOP register at address 0x003C are loaded from the Flash configuration field byte at global address 0x3_FF0E during the reset sequence See Table 1 13 and Table 1 14 for coding Table 1 12 Usage of ADC Special Conversion Channels...

Page 45: ...part dependent and should thus be calibrated 1 12 7 Flash IFR Mapping Table 1 14 Initial WCOP Configuration NV 3 in FOPT Register WCOP in COPCTL Register 1 0 0 1 Table 1 15 Flash IFR Mapping IFR Byte Address F E D C B A 9 8 7 6 5 4 3 2 1 0 0x40B8 0x40B9 ACLKTR 5 0 1 1 see Section 4 3 2 16 Autonomous Clock Trimming Register CPMUACLKTR HTTR 3 0 2 2 see Section 4 3 2 19 High Temperature Trimming Regi...

Page 46: ...Device Overview S12VRP Series MC9S12VRP Family Reference Manual Rev 1 3 46 NXP Semiconductors ...

Page 47: ...outed to 2 pins simultaneously V00 06 28 Apr 2016 Moved API_EXTCLK to PS2 following DFT feedback Replaced PT2 with PS2 in DFT port following DFT feedback V00 07 10 May 2016 2 3 2 8 68 Specified pin interrupt and ETRIG timing specs invalid if RCOEN is set V00 08 07 Jul 2016 Various Table 2 6 Table 2 7 Table 2 8 Table 2 9 Table 2 10 Table 2 11 Table 2 12 Minor enhancements and fixes from RM V1 0A sh...

Page 48: ...heral modules and the I O pins for all ports It controls the electrical pin properties as well as the signal prioritization and multiplexing on shared pins This document covers Port AD Port E Port L GPIO KWU ADC AMP Pins PTAD5 AN5 PAD5 PTAD4 AN4 PAD4 PTAD3 AN3 PAD3 PTAD2 AN2 AMPP0 PAD2 PTAD1 AN1 AMPM0 PAD1 PTAD0 AN0 AMP0 PAD0 GPIO External Oscillator Pins PTE1 XTAL PE1 PTE0 EXTAL PE0 HVI KWU ADC P...

Page 49: ...3 AN9 PL3 PTIL2 AN8 PL2 PTIL1 AN7 PL1 PTIL0 AN6 PL0 GPIO KWU ETRIG PWM IRQ XIRQ Pins PTP5 ETRIG1 PWM5 IRQ PP5 PTP4 ETRIG0 PWM4 PP4 PTP3 PWM3 PP3 PTP2 PWM2 PP2 PTP1 PWM1 XIRQ PP1 PTP0 PWM0 PP0 GPIO ETRIG PWM SCI0 LINPHY SCI1 CLOCK Pins PTS3 ETRIG1 PWM5 TXD1 ECLK PS3 PTS2 ETRIG0 PWM4 RXD1 PS2 PTS1 TXD0 LPDR1 TXD1 PS1 PTS0 RXD0 RXD1 PS0 ...

Page 50: ...llups or pulldowns on ports AD S T P Control registers to enable open drain wired or mode on port S Control register to enable disable reduced output drive on port P high current pins Control register to enable digital input buffers on port L Interrupt enable register for pin interrupts and key wakeup KWU on ports AD P and L Interrupt flag register for pin interrupts and key wakeup KWU on ports AD...

Page 51: ...otection High voltage input 2 2 External Signal Description This section lists and describes the signals that connect off chip Table 2 10 shows all pins and functions that are controlled by the PIM Routing options are denoted in parentheses Specific functions cannot be routed to 2 pins simultaneously NOTE If there is more than one function associated with a pin the output priority is indicated by ...

Page 52: ...ister 3 ATDCTL3 PTAD 5 3 KWAD 5 3 I O GPIO with pin interrupt and key wakeup PAD2 AMPP0 I ISENSE AMP0 non inverting input AN2 I ADC analog input PTAD 2 KWAD 2 I O GPIO with pin interrupt and key wakeup PAD1 AMPM0 I ISENSE AMP0 inverting input AN1 I ADC analog input PTAD 1 KWAD 1 I O GPIO with pin interrupt and key wakeup PAD0 AMP0 O ISENSE AMP0 output AN0 I ADC analog input PTAD 0 KWAD 0 I O GPIO ...

Page 53: ... pin interrupt with key wakeup and ADC analog input HVI PL4 PTL 4 KWL 4 AN10 I HVI with pin interrupt with key wakeup and ADC analog input PL3 PTL 3 KWL 3 AN9 I HVI with pin interrupt with key wakeup and ADC analog input PL2 PTL 2 KWL 2 AN8 I HVI with pin interrupt with key wakeup and ADC analog input PL1 PTL 1 KWL 1 AN7 I HVI with pin interrupt with key wakeup and ADC analog input PL0 PTL 0 KWL 0...

Page 54: ...gger input PWM4ET0 PTP 4 KWP 4 I O GPIO with pin interrupt and key wakeup PP3 PWM3 O PWM channel 3 HS0RR1 0 PTP 3 KWP 3 I O GPIO with pin interrupt and key wakeup PP2 PWM2 O PWM channel 2 with over current interrupt LS2RR1 0 PTP 2 KWP 2 EVDD I O GPIO with interrupt and wakeup Switchable external power supply output 20mA with over current interrupt PP1 XIRQ I Non maskable level sensitive interrupt ...

Page 55: ...egister LPDR LPDR1 MODRR23 20 TXD0 I O SCI0 transmit MODRR23 20 PTS 1 I O GPIO PS0 RXD1 I SCI1 receive MODRR24 RXD0 I SCI0 receive MODRR23 20 PTS 0 I O GPIO Port Pin Pin Function Priority I O Description Routing Register Bit Func after Reset T PT3 LPTXD I LINPHY transmit pin MODRR23 20 GPIO IOC1_1 I O TIM1 channel 1 HS1RR1 0 OC1_1 LS2RR1 0 OC1_1 MODRR27 IC1_1 PTT 3 I O GPIO PT2 API1 O CPMU API ext...

Page 56: ...fer to section S12HSDRV HS1 PWM1 O PWM channel 1 HS1RR1 0 HSDRV PWM4 O PWM channel 4 HS1RR1 0 OC1_1 O TIM1 output compare channel 1 HS1RR1 0 LS2RR1 0 HSDR HSDR1 O High side driver 1 HS1RR1 0 HS0 PWM3 O PWM channel 3 HS0RR1 0 HSDRV OC1_0 O TIM1 output compare channel 0 HS0RR1 0 HSDR HSDR0 O High side driver 0 HS0RR1 0 Port Pin Pin Function No Priority 1 1 No priority The routing is selected solely ...

Page 57: ...PEE 0 0 0 0 W 0x000D Reserved R Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved W 0x000E 0x001B Non PIM Address Range R Non PIM Address Range W 0x001C ECLKCTL R NECLK 0 0 0 0 0 0 0 W 0x001D PPOCPE R OCPEP2 OCPEP0 0 0 0 0 0 0 W 0x001E IRQCR R IRQE IRQEN 0 0 0 0 0 0 W 0x001F Reserved R Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved W 0x0020 0x023F Non...

Page 58: ...0 0 0 0 PTS3 PTS2 PTS1 PTS0 W 0x0249 PTIS R 0 0 0 0 PTIS3 PTIS2 PTIS1 PTIS0 W 0x024A DDRS R 0 0 0 0 DDRS3 DDRS2 DDRS1 DDRS0 W 0x024B Reserved R 0 0 0 0 0 0 0 0 W 0x024C PERS R 0 0 0 0 PERS3 PERS2 PERS1 PERS0 W 0x024D PPSS R 0 0 0 0 PPSS3 PPSS2 PPSS1 PPSS0 W 0x024E WOMS R 0 0 0 0 WOMS3 WOMS2 WOMS1 WOMS0 W 0x024F MODRR2 R MODRR27 0 0 MODRR24 MODRR23 MODRR22 MODRR21 MODRR20 W 0x0250 0x0257 Reserved R...

Page 59: ...ed Reserved Reserved Reserved Reserved Reserved Reserved W 0x0261 0x0264 Reserved R 0 0 0 0 0 0 0 0 W 0x0265 PTAENL R 0 0 PTAENL5 PTAENL4 PTAENL3 PTAENL2 PTAENL1 PTAENL0 W 0x0266 PTADIRL R 0 0 PTADIRL5 PTADIRL4 PTADIRL3 PTADIRL2 PTADIRL1 PTADIRL0 W 0x0267 PTABYPL R 0 0 PTABYPL5 PTABYPL4 PTABYPL3 PTABYPL2 PTABYPL1 PTABYPL0 W 0x0268 PTPSL R 0 0 PTPSL5 PTPSL4 PTPSL3 PTPSL2 PTPSL1 PTPSL0 W 0x0269 PTIL...

Page 60: ... 0 0 W 0x0273 PTI1AD R 0 0 PTI1AD5 PTI1AD4 PTI1AD3 PTI1AD2 PTI1AD1 PTI1AD0 W 0x0274 Reserved R 0 0 0 0 0 0 0 0 W 0x0275 DDR1AD R 0 0 DDR1AD5 DDR1AD4 DDR1AD3 DDR1AD2 DDR1AD1 DDR1AD0 W 0x0276 0x0278 Reserved R 0 0 0 0 0 0 0 0 W 0x0279 PER1AD R 0 0 PER1AD5 PER1AD4 PER1AD3 PER1AD2 PER1AD1 PER1AD0 W 0x027A Reserved R 0 0 0 0 0 0 0 0 W 0x027B PPS1AD R 0 0 PPS1AD5 PPS1AD4 PPS1AD3 PPS1AD2 PPS1AD1 PPS1AD0 ...

Page 61: ...read write1 1 Read Anytime Write Once in normal anytime in special mode 7 6 5 4 3 2 1 0 R 0 0 LS2RR1 LS2RR0 LS1RR1 LS1RR0 LS0RR1 LS0RR0 W Reset 0 0 0 0 0 0 0 0 Figure 2 1 Module Routing Register 0 Table 2 11 Module Routing Register 0 Field Descriptions Field Description 5 4 LS2RR1 0 MODule Routing Register 0 LS2 This register controls the routing of PWM and TIM channels to pin LS2 of LS2DRV module...

Page 62: ...outed to LS0 if enabled 01 TIM0 output compare channel 0 routed to LS0 if enabled 00 LS0 controlled by register bit LSDR LSDR0 Refer to LSDRV section Address 0x0247 Access User read write1 1 Read Anytime Write Once in normal anytime in special mode 7 6 5 4 3 2 1 0 R 0 0 PWM5ET1 PWM4ET0 HS1RR1 HS1RR0 HS0RR1 HS0RR0 W Reset 0 0 0 0 0 0 0 0 Figure 2 2 Module Routing Register 1 MODRR1 Table 2 12 MODRR1...

Page 63: ...SDRV port register bit 11 PWM channel 3 routed to HS0 if enabled 10 PWM channel 3 routed to HS0 if enabled 01 TIM1 output compare channel 0 routed to HS0 if enabled 00 HS0 controlled by register bit HSDR HSDR0 Refer to HSDRV section Address 0x024F Access User read write1 1 Read Anytime Write Once in normal anytime in special mode 7 6 5 4 3 2 1 0 R MODRR27 0 0 MODRR24 MODRR23 MODRR22 MODRR21 MODRR2...

Page 64: ...onformance testing Refer to Figure 2 4 for an illustration and Table 2 14 for preferred settings SCI0 must be enabled for TXD0 routing to take effect on pins LINPHY must be enabled for LPRXD and LPDR LPDR1 routings to take effect on pins MODRR2 2 0 Description 000 Default setting SCI0 connects to LINPHY interface internal only 001 Direct control setting LPDR LPDR1 register bit controls LPTXD inter...

Page 65: ... 6 5 4 3 2 1 0 R 0 BKPUE 0 PDPEE 0 0 0 0 W Reset 0 1 0 1 0 0 0 0 Figure 2 5 Port E BKGD pin Pull Control Register PUCR Table 2 15 PUCR Register Field Descriptions Field Description 6 BKPUE BKGD pin Pullup Enable Activate pullup device on pin This bit configures whether a pull up device is activated if the pin is used as input If a pin is used as output this bit has no effect 1 Pullup device enable...

Page 66: ... Anytime Write Only in special mode This reserved register is designed for factory test purposes only and is not intended for general user access Writing to this register when in special modes can alter the module s functionality 7 6 5 4 3 2 1 0 R Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved W Reset x x x x x x x x Figure 2 6 Reserved Register ...

Page 67: ...ed rate equivalent to the internal bus clock 1 ECLK disabled 0 ECLK enabled Address 0x001E Access User read write1 1 Read Anytime Write IRQE Once in normal mode anytime in special mode IRQEN Anytime 7 6 5 4 3 2 1 0 R IRQE IRQEN 0 0 0 0 0 0 W Reset 0 0 0 0 0 0 0 0 Figure 2 8 IRQ Control Register IRQCR Table 2 17 IRQCR Register Field Descriptions Field Description 7 IRQE IRQ select edge sensitive on...

Page 68: ...l register read accesses are synchronous to internal clocks All registers can be written at any time however a specific configuration might not become active E g a pull up device does not become active while the port is used as a push pull output General purpose data output availability depends on prioritization input data registers always reflect the pin status independent of the use Address 0x00...

Page 69: ... 7 6 5 4 3 2 1 0 R PTx7 PTx6 PTx5 PTx4 PTx3 PTx2 PTx1 PTx0 W Reset 0 0 0 0 0 0 0 0 Figure 2 11 Port Data Register Table 2 18 Port Data Register Field Descriptions Field Description 7 0 PTx7 0 Port Data General purpose input output data This register holds the value driven out to the pin if the pin is used as a general purpose output When not used with the alternative function refer to Table 2 10 t...

Page 70: ... 0 0 0 0 0 0 0 Figure 2 13 Data Direction Register Table 2 20 Data Direction Register Field Descriptions Field Description 7 0 DDRx7 0 Data Direction Select general purpose data direction This bit determines whether the pin is a general purpose input or output If a peripheral module controls the pin the content of the data direction register is ignored Independent of the pin usage with a periphera...

Page 71: ...d Description 7 0 PERx7 0 Pull Enable Activate pull device on input pin This bit controls whether a pull device on the associated port input or open drain output pin is active The PERS 3 0 reset value is 0xF All other bits reset to 0 If a pin is used as push pull output this bit has no effect The polarity is selected by the related polarity select register bit On open drain output pins only a pull...

Page 72: ...L Access User read write1 1 Read Anytime Write Anytime 7 6 5 4 3 2 1 0 R PIEx7 PIEx6 PIEx5 PIEx4 PIEx3 PIEx2 PIEx1 PIEx0 W Reset 0 0 0 0 0 0 0 0 Figure 2 16 Port Interrupt Enable Register Table 2 23 Port Interrupt Enable Register Field Descriptions Field Description 7 0 PIEx7 0 Port Interrupt Enable Activate pin interrupt KWU This bit enables or disables the edge sensitive pin interrupt on the ass...

Page 73: ...ng a logic 1 to the corresponding bit field clears the flag 1 Active edge on the associated bit has occurred 0 No active edge occurred Address 0x025B RDRP Access User read write1 1 Read Anytime Write Anytime 7 6 5 4 3 2 1 0 R RDRx7 RDRx6 RDRx5 RDRx4 RDRx3 RDRx2 RDRx1 RDRx0 W Reset 0 0 0 0 0 0 0 0 Figure 2 18 Reduced Drive Register Table 2 25 Reduced Drive Register Field Descriptions Field Descript...

Page 74: ...9 Wired Or Mode Register Table 2 26 Wired Or Mode Register Field Descriptions Field Description 7 0 WOMx7 0 Wired Or Mode register Enable open drain output This bit configures an output pin as wired or If enabled the output is driven active low only open drain while the active high drive is disabled This allows a multi point connection of several serial modules The bit has no influence on pins use...

Page 75: ... Field Description 7 OCPEP2 Over Current Protection Enable Port P 2 Activate over current detector on PP2 refer to 2 5 3 Over Current Protection on PP2 and PP0 1 PP2 over current detector enabled 0 PP2 over current detector disabled 6 OCPEP0 Over Current Protection Enable Port P 0 Activate over current detector on PP0 refer to 2 5 3 Over Current Protection on PP2 and PP0 1 PP0 over current detecto...

Page 76: ...it enables or disables the edge sensitive pin interrupt on the associated pin An interrupt can be generated if the pin is operating in input or output mode when in use with the general purpose or related peripheral function 1 Interrupt is enabled 0 Interrupt is disabled interrupt flag masked Address 0x025F PIFP Access User read write1 1 Read Anytime Write Anytime write 1 to clear 7 6 5 4 3 2 1 0 R...

Page 77: ...iated interrupt enable bit is set Writing a logic 1 to the corresponding bit field clears the flag 1 Active edge on the associated bit has occurred 0 No active edge occurred Address 0x0265 Access User read write1 1 Read Anytime Write Anytime 7 6 5 4 3 2 1 0 R 0 0 PTAENL5 PTAENL4 PTAENL3 PTAENL2 PTAENL1 PTAENL0 W Reset 0 0 0 0 0 0 0 0 Figure 2 24 Port L ADC Connection Enable Register PTAENL Table 2...

Page 78: ...ing the voltage divider This bit takes effect only in analog mode PTAENL 1 1 Input pin directly connected to ADC channel 0 Input voltage divider active on analog input to ADC channel Address 0x0267 Access User read write1 1 Read Anytime Write Anytime 7 6 5 4 3 2 1 0 R 0 0 PTABYPL5 PTABYPL4 PTABYPL3 PTABYPL2 PTABYPL1 PTABYPL0 W Reset 0 0 0 0 0 0 0 0 Figure 2 26 Port L ADC Bypass Register PTABYPL Ta...

Page 79: ...age divider If this bit set to 1 and PTTEL 1 and not in stop mode a pull up to a level close to VDDX takes effect and overrides the weak pulldown device 1 Pullup enabled 0 Pulldown enabled Address 0x0269 Access User read only1 1 Read Anytime Write Never 7 6 5 4 3 2 1 0 R 0 0 PTIL5 PTIL4 PTIL3 PTIL2 PTIL1 PTIL0 W Reset 0 0 0 0 0 0 0 0 Figure 2 28 Port L Input Register PTIL Table 2 34 PTIL Register ...

Page 80: ...on 5 0 DIENL5 0 Digital Input Enable Port L Input buffer control This bit controls the HVI digital input function If set to 1 the input buffer is enabled and the HVI pin can be used with the digital function If the analog input function is enabled PTAENL 1 the input buffer of the selected HVI pin is forced off1 in run mode and is released to be active in stop mode only if DIENL 1 1 Associated pin ...

Page 81: ...4 PTTEL3 PTTEL2 PTTEL1 PTTEL0 W Reset 0 0 0 0 0 0 0 0 Figure 2 30 Port L Test Enable Register PTTEL Table 2 36 PTTEL Register Field Descriptions Field Description 5 0 PTTEL5 0 Port L Test Enable This bit forces the input buffer of the HVI pin active while using the analog function to support open input detection in run mode Refer to Section 2 5 4 Open Input Detection on PL 5 0 HVI In stop mode thi...

Page 82: ...ort L Input Divider Ratio Selection Register PIRL Table 2 37 PIRL Register Field Descriptions Field Description 5 0 PIRL5 0 Port L Input Divider Ratio Select This bit selects one of two voltage divider ratios for the associated HVI pin in analog mode 1 RatioL_HVI selected 0 RatioH_HVI selected Address 0x026D Access User read write1 1 Read Anytime Write Anytime 7 6 5 4 3 2 1 0 R 0 0 PPSL5 PPSL4 PPS...

Page 83: ...ed as general purpose I O or with a shared peripheral function If the pin is configured as input DDRx 0 Section 2 3 3 3 Data Direction Register the pin state can also be read through the data register PTx Section 2 3 3 1 Port Data Register Table 2 39 Bit Indices of Implemented Register Bits per Port Port Data Register Port Input Register Data Direction Register Pull Device Enable Register Polarity...

Page 84: ...atures Enabled Feature1 1 If applicable the appropriate routing configuration must be set for the signals to take effect on the pins Related Signal s Effect on I O state CPMU OSC EXTAL XTAL CPMU takes control TIMx output compare y IOCx_y Forced output TIMx input capture y IOCx_y None2 2 DDR maintains control SCIx TXDx SCI takes control RXDx Forced input PWM channel x PWMx Forced output ADC channel...

Page 85: ...ng bit in the RDRP register Section 2 3 3 8 Reduced Drive Register The drive strength is independent of the pin being used by peripheral modules These pins can be used as general purpose I O or due to increased current capability in output mode as switchable external power supply EVDD pins for external devices like Hall sensors PP2 is a nominally 20mA capable pin on high and low sides It includes ...

Page 86: ...ort interrupt flag PIF and its corresponding port interrupt enable PIE are both set The pin interrupt feature is also capable of waking up the CPU when it is in stop or wait mode key wakeup A digital filter on each pin prevents short pulses from generating an interrupt A valid edge on an input is detected if 4 consecutive samples of a passive level are followed by 4 consecutive samples of an activ...

Page 87: ...tect the device The flag must be cleared to re enable the driver 2 4 8 High Voltage Input A high voltage input HVI on port L has the following features Input voltage range up to VLX Digital input function Pin interrupt and wakeup from stop capability Analog input function with selectable divider ratio and interface to ADC channels Optional direct input bypassing voltage divider and impedance conve...

Page 88: ... There are two modes digital and analog where these signals can be processed 2 4 8 1 Digital Mode Operation In digital mode PTAENL 0 the input buffer is enabled if DIENL 1 The synchronized pin input state determined at threshold level VTH_HVI can be read in register PTIL An interrupt flag PIFL is set on input transitions if enabled PIEL 1 and configured for the related edge polarity PPSL Wakeup fr...

Page 89: ...peration mode 2 5 Initialization and Application Information 2 5 1 Port Data and Data Direction Register writes It is not recommended to write PORTx PTx and DDRx in a word access When changing the register pins from inputs to outputs the data may have extra transitions during the write access Initialize the port data register before enabling the outputs 2 5 2 SCI Baud Rate Detection The baud rate ...

Page 90: ...down prior to entering stop mode by driving the output low An over current condition is detected if the output current level exceeds the threshold IOCD in run mode The output driver is immediately forced low and the over current interrupt flag OCIF asserts Refer to Section 2 4 7 3 Over Current Interrupt and Protection 2 5 4 Open Input Detection on PL 5 0 HVI The connection of an external pull devi...

Page 91: ...PTADIRL 0 2 Select internal pulldown device on HVI PTPSL 0 3 Enable function to force input buffer active on HVI in analog mode PTTEL 1 4 Verify PTIL 1 for a connected external pull up device read PTIL 0 for an open input Figure 2 37 Digital Input Read with Pulldown Enabled HVI 140K 400K VDDX Digital in 110K 550K min 1 4 VDDX 10K PIRL 0 PIRL 1 HV Supply HVI 140K 510K 950K Digital in max 17 22 VHVI...

Page 92: ...Port Integration Module S12VRPPIMV1 MC9S12VRP Family Reference Manual Rev 1 3 92 NXP Semiconductors ...

Page 93: ...thermore the S12GMMC is responsible for constraining memory accesses on secured devices and for selecting the MCU s functional mode Rev No Item No Date Submitted By Sections Affected Substantial Change s 01 04 26 Apr 2016 Added S12VRP64 Table 3 2 Glossary Of Terms Term Definition Local Addresses Address within the CPU12 s Local Address Map Figure 3 12 Global Address Address within the Global Addre...

Page 94: ...on The S12GMMC selects the MCU s functional mode It also determines the devices behavior in secured and unsecured state 3 1 4 1 Functional Modes Two functional modes are implemented on devices of the S12VRP product family Normal Single Chip NS The mode used for running applications Special Single Chip Mode SS A debug mode which causes the device to enter BDM Active Mode after each reset Peripheral...

Page 95: ...ry of the registers associated with the S12GMMC block is shown in Figure 3 2 Detailed descriptions of the registers and bits are given in the subsections that follow Table 3 3 External System Pins Associated With S12GMMC Pin Name Pin Functions Description RESET See Section Device Overview RESET The RESET pin is used the select the MCU s operating mode MODC See Section Device Overview MODC The MODC...

Page 96: ...MODC 0 0 0 0 0 0 0 W 0x0010 Reserved R 0 0 0 0 0 0 0 0 W 0x0011 DIRECT R DP15 DP14 DP13 DP12 DP11 DP10 DP9 DP8 W 0x0012 Reserved R 0 0 0 0 0 0 0 0 W 0x0013 MMCCTL1 R 0 0 0 0 0 0 0 NVMRES W 0x0014 Reserved R 0 0 0 0 0 0 0 0 W 0x0015 PPAGE R 0 0 0 0 PIX3 PIX2 PIX1 PIX0 W 0x0016 0x0017 Reserved R 0 0 0 0 0 0 0 0 W Unimplemented or Reserved Figure 3 2 MMC Register Summary Address 0x000B 7 6 5 4 3 2 1 ...

Page 97: ...t Bit This bit controls the current operating mode during RESET high inactive The external mode pin MODC determines the operating mode during RESET low active The state of the pin is registered into the respective register bit after the RESET signal goes inactive see Figure 3 4 Write restrictions exist to disallow transitions between certain modes Figure 3 4 illustrates all allowed mode changes At...

Page 98: ...o 0x07FFF Table 3 5 DIRECT Field Descriptions Field Description 7 0 DP 15 8 Direct Page Index Bits 15 8 These bits are used by the CPU when performing accesses using the direct addressing mode These register bits form bits 15 8 of the local address see Figure 3 6 Address 0x0013 7 6 5 4 3 2 1 0 R 0 0 0 0 0 0 0 NVMRES W Reset 0 0 0 0 0 0 0 0 Unimplemented or Reserved Figure 3 7 MMC Control Register ...

Page 99: ...ites to this register using the special access of the CALL and RTC instructions will be complete before the end of the instruction execution The fixed 16KB page from 0x0000 to 0x3FFF is the page number 0xC Parts of this page are covered by Registers D Flash and RAM space See SoC Guide for details The fixed 16KB page from 0x4000 0x7FFF is the page number 0xD Address 0x0015 7 6 5 4 3 2 1 0 R 0 0 0 0...

Page 100: ...ns share addresses with other modules however they are not visible in the memory map during user s code execution The BDM memory resources are enabled only during the READ_BD and WRITE_BD access cycles to distinguish between accesses to the BDM memory area and accesses to the other modules Refer to BDM Block Guide for further details When the MCU enters active BDM mode the BDM firmware lookup tabl...

Page 101: ...s that are in paged memory The upper 16KB block of the local CPU memory space 0xC000 0xFFFF is unpaged It is recommended that all reset and interrupt vectors point to locations in this area or to the other unmapped pages sections of the local CPU memory map Expansion of the BDM Local Address Map PPAGE and BDMPPR register is also used for the expansion of the BDM local address to the global address...

Page 102: ...l Rev 1 3 102 NXP Semiconductors Figure 3 10 Figure 3 11 BDM HARDWARE COMMAND BDM FIRMWARE COMMAND Bit14 Bit0 BDM Local Address 13 0 BDMPPR Register 3 0 Global Address 17 0 Bit13 Bit17 Bit14 Bit0 CPU Local Address 13 0 BDMPPR Register 3 0 Global Address 17 0 Bit13 Bit17 ...

Page 103: ...sh Space P Flash Space Flash Space Flash Space Register Space Register Space Internal NVM Resources Internal NVM Resources D Flash Page 0x1 Page 0x1 Page 0xF Page 0xF Page 0xD Page 0xD Register Space Register Space Page 0xC Page 0xC Page 0xE Page 0xE Page 0xF Page 0xF Page 0xD Page 0xD Page 0xC Page 0xC NVMRES 0 NVMRES 0 NVMRES 1 NVMRES 1 Page 0x2 Page 0x2 0x3_0000 0x3_4000 0x3_8000 0x0_8000 RAM R...

Page 104: ...y are attempted by the CPU The BDM is not able to trigger illegal address resets Reserved addresses are associated with a memory block on the device even though the memory block does not contain the resources to fill the address space The S12GMMC is not aware that the associated memory does not physically exist It does not trigger an illegal address reset when accesses to reserved locations are at...

Page 105: ...not able to access the memory in parallel An arbitration occurs whenever both modules attempt a memory access at the same time CPU accesses are handled with higher priority than BDM accesses unless the BDM module has been stalled for more then 128 bus cycles In this case the pending BDM access will be processed immediately 3 4 5 Interrupts The S12GMMC does not generate any interrupts ...

Page 106: ...S12G Memory Map Controller S12GMMCV1 MC9S12VRP Family Reference Manual Rev 1 3 106 NXP Semiconductors ...

Page 107: ...v No Item No Date Submitted By Sections Affected Substantial Change s V08 00 27 Jan 14 Added full swing pierce oscillator OSCMOD bit in CPMUOSC2 register Added drawing in Block Diagram Added oscillator clock monitor reset to be configured with OMRE bit CPMUOSC2 register Added drawing in Block Diagram Added PLL clock monitor reset and PMRF flag in CPMUINT register Added drawing in Block Diagram V08...

Page 108: ...reased emission The Voltage Regulator VREGAUTO has the following features Input voltage range from 6 to 18V nominal operating range Low voltage detect LVD with low voltage interrupt LVI Power on reset POR Low voltage reset LVR On Chip Temperature Sensor and Bandgap Voltage measurement via internal ADC channel High temperature interrupt Voltage Regulator providing Full Performance Mode FPM and Redu...

Page 109: ...ed by overwriting the IRCTRIM register Other features of the S12CPMU_UHV_V8 include Autonomous periodical interrupt API Bus Clock Generator Clock switch to select either PLLCLK or external crystal resonator based Bus Clock PLLCLK divider to adjust system speed System Reset generation from the following possible sources Power on reset POR Low voltage reset LVR Illegal address access COP time out Lo...

Page 110: ...MHz VCOCLK operation Post divider is 0x03 so PLLCLK is VCOCLK divided by 4 that is 12 5MHz and Bus Clock is 6 25MHz The PLL can be re configured for other bus frequencies The reference clock for the PLL REFCLK is based on internal reference clock IRC1M PLL Engaged External PEE The Bus Clock is based on the PLLCLK This mode can be entered from default mode PEI by performing the following steps Conf...

Page 111: ...set LVR are disabled The API is available The Phase Locked Loop PLL is off The Internal Reference Clock IRC1M is off Core Clock Bus Clock and BDM Clock are stopped Depending on the setting of the PSTP and the OSCE bit Stop Mode can be differentiated between Full Stop Mode PSTP 0 or OSCE 0 and Pseudo Stop Mode PSTP 1 and OSCE 1 In addition the behavior of the COP in each mode will change based on t...

Page 112: ...K for the COP can be stopped COP static or running COP active depending on the setting of bit CSAD When bit CSAD is set the ACLK for the COP is stopped during Pseudo Stop Mode and COP continues to operate after exit from Pseudo Stop Mode For this COP configuration ACLK clock source CSAD set a latency time please refer to CSAD bit description for details occurs when entering or exiting Pseudo Full ...

Page 113: ...o 18V Autonomous Periodic Interrupt API API Interrupt VSS PLLSEL VSSX VDDA VDDX Low Voltage Detect VDDX LVRF PLLCLK Reference divide by 8 BDM Clock Clock IRC1M Clock Monitor OSC monitor fail Real Time Interrupt RTI RTI Interrupt PSTP CPMURTI Oscillator status Interrupt XOSCLCP High Temperature Sense HT Interrupt Low Voltage Interrupt APICLK RTICLK IRCCLK OSCCLK RTIOSCSEL COP time out PRE UPOSC 0 s...

Page 114: ...eference Manual Rev 1 3 114 NXP Semiconductors Figure 4 2 shows a block diagram of the XOSCLCP Figure 4 2 XOSCLCP Block Diagram EXTAL XTAL Gain Control VDD 1 8 V Rf OSCCLK_LCP Peak Detector VSS VSS VSS C1 C2 Quartz Crystals Ceramic Resonators or Clock Monitor OSC monitor fail ...

Page 115: ...proximately 700 k NOTE Freescale recommends an evaluation of the application board and chosen resonator or crystal by the resonator or crystal supplier The loop controlled circuit XOSCLCP is not suited for overtone resonators and crystals 4 2 3 VSUP Regulator Power Input Pin Pin VSUP is the power input of VREGAUTO All currents sourced into the regulator loads flow through this pin An appropriate r...

Page 116: ...ernal Regulator Output Supply Core Logic Node VDD is a device internal supply output of the voltage regulator that provides the power supply for the core logic This supply domain is monitored by the Low Voltage Reset circuit 4 2 9 VDDF Internal Regulator Output Supply NVM Logic Node VDDF is a device internal supply output of the voltage regulator that provides the power supply for the NVM logic Th...

Page 117: ...F LVRF LOCKIF LOCK ILAF OSCIF UPOSC W 0x0038 CPMUINT R RTIE 0 0 LOCKIE 0 0 OSCIE PMRF W 0x0039 CPMUCLKS R PLLSEL PSTP CSAD COP OSCSEL1 PRE PCE RTI OSCSEL COP OSCSEL0 W 0x003A CPMUPLL R 0 0 FM1 FM0 0 0 0 0 W 0x003B CPMURTI R RTDEC RTR6 RTR5 RTR4 RTR3 RTR2 RTR1 RTR0 W 0x003C CPMUCOP R WCOP RSBCK 0 0 0 CR2 CR1 CR0 W WRTMASK 0x003D RESERVED CPMUTEST0 R 0 0 0 0 0 0 0 0 W 0x003E RESERVED CPMUTEST1 R 0 0...

Page 118: ... APIR3 APIR2 APIR1 APIR0 W 0x02F6 RESERVED CPMUTEST3 R 0 0 0 0 0 0 0 0 W 0x02F7 CPMUHTTR R HTOE 0 0 0 HTTR3 HTTR2 HTTR1 HTTR0 W 0x02F8 CPMU IRCTRIMH R TCTRIM 4 0 0 IRCTRIM 9 8 W 0x02F9 CPMU IRCTRIML R IRCTRIM 7 0 W 0x02FA CPMUOSC R OSCE 0 0 0 0 0 0 0 W 0x02FB CPMUPROT R 0 0 0 0 0 0 0 PROT W 0x02FC RESERVED CPMUTEST2 R 0 0 0 0 0 0 0 0 W 0x02FD RESERVED R 0 0 0 0 0 0 0 0 W 0x02FE CPMUOSC2 R 0 0 0 0 ...

Page 119: ... and UPOSC status bits NOTE fVCO must be within the specified VCO frequency lock range Bus frequency fbus must not exceed the specified maximum The VCOFRQ 1 0 bits are used to configure the VCO gain for optimal stability and lock time For correct PLL operation the VCOFRQ 1 0 bits have to be selected according to the actual target VCOCLK frequency as shown in Table 4 2 Setting the VCOFRQ 1 0 bits i...

Page 120: ...on the REFFRQ 1 0 bits have to be selected according to the actual REFCLK frequency as shown in Table 4 3 If IRC1M is selected as REFCLK OSCE 0 the PLL filter is fixed configured for the 1MHz fREF 2MHz range The bits can still be written but will have no effect on the PLL filter configuration For OSCE 1 setting the REFFRQ 1 0 bits incorrectly can result in a non functional PLL no locking and or in...

Page 121: ...2 1 0 R 0 0 0 POSTDIV 4 0 W Reset 0 0 0 0 0 0 1 1 Unimplemented or Reserved Figure 4 6 S12CPMU_UHV_V8 Post Divider Register CPMUPOSTDIV 0x0037 7 6 5 4 3 2 1 0 R RTIF PORF LVRF LOCKIF LOCK ILAF OSCIF UPOSC W Reset 0 Note 1 Note 2 0 0 Note 3 0 0 1 PORF is set to 1 when a power on reset occurs Unaffected by System Reset 2 LVRF is set to 1 when a low voltage reset occurs Unaffected by System Reset Set...

Page 122: ... causes an interrupt request 0 No change in LOCK bit 1 LOCK bit has changed 3 LOCK Lock Status Bit LOCK reflects the current state of PLL lock condition Writes have no effect While PLL is unlocked LOCK 0 fPLL is fVCO 4 to protect the system from high core clock frequencies during the PLL stabilization time tlock 0 VCOCLK is not within the desired tolerance of the target frequency fPLL fVCO 4 1 VCO...

Page 123: ...egister CPMUINT Table 4 5 CPMUINT Field Descriptions Field Description 7 RTIE Real Time Interrupt Enable Bit 0 Interrupt requests from RTI are disabled 1 Interrupt will be requested whenever RTIF is set 4 LOCKIE PLL Lock Interrupt Enable Bit 0 PLL LOCK interrupt requests are disabled 1 Interrupt will be requested whenever LOCKIF is set 1 OSCIE Oscillator Corrupt Interrupt Enable Bit 0 Oscillator C...

Page 124: ... 0 until CPMUCOP write once has taken place COPOSCSEL1 will not be cleared by UPOSC 0 entering Full Stop Mode with COPOSCSEL1 1 or insufficient OSCCLK quality if OSCCLK is used as clock source for other clock domains for instance core clock etc NOTE After writing CPMUCLKS register it is strongly recommended to read back CPMUCLKS register to make sure that write of PLLSEL RTIOSCSEL and COPOSCSEL wa...

Page 125: ...re is a latency time of 2 ACLK cycles to enter Stop Mode After exit from STOP mode when interrupt service routine is entered the software has to wait for 2 ACLK cycles before it is allowed to enter Stop mode again STOP instruction It is absolutely forbidden to enter Stop Mode before this time of 2 ACLK cycles has elapsed 0 COP running in Stop Mode ACLK for COP enabled in Stop Mode 1 COP stopped in...

Page 126: ...COP OSCSEL0 COP Clock Select 0 COPOSCSEL0 and COPOSCSEL1 combined determine the clock source to the COP see also Table 4 7 If COPOSCSEL1 1 COPOSCSEL0 has no effect regarding clock select and changing the COPOSCSEL0 bit does not re start the COP time out period When COPOSCSEL1 0 COPOSCSEL0 selects the clock source to the COP to be either IRCCLK or OSCCLK Changing the COPOSCSEL0 bit re starts the CO...

Page 127: ...hould be taken to ensure that the bus frequency does not exceed the specified maximum when frequency modulation is enabled 0x003A 7 6 5 4 3 2 1 0 R 0 0 FM1 FM0 0 0 0 0 W Reset 0 0 0 0 0 0 0 0 Figure 4 10 S12CPMU_UHV_V8 PLL Control Register CPMUPLL Table 4 8 CPMUPLL Field Descriptions Field Description 5 4 FM1 FM0 PLL Frequency Modulation Enable Bits FM1 and FM0 enable frequency modulation on the V...

Page 128: ...oosing UPOSC status re starts the RTI time out period 0x003B 7 6 5 4 3 2 1 0 R RTDEC RTR6 RTR5 RTR4 RTR3 RTR2 RTR1 RTR0 W Reset 0 0 0 0 0 0 0 0 Figure 4 11 S12CPMU_UHV_V8 RTI Control Register CPMURTI Table 4 10 CPMURTI Field Descriptions Field Description 7 RTDEC Decimal or Binary Divider Select Bit RTDEC selects decimal or binary based prescaler values 0 Binary based divider value See Table 4 11 ...

Page 129: ...F 4x210 4x211 4x212 4x213 4x214 4x215 4x216 0100 5 OFF 5x210 5x211 5x212 5x213 5x214 5x215 5x216 0101 6 OFF 6x210 6x211 6x212 6x213 6x214 6x215 6x216 0110 7 OFF 7x210 7x211 7x212 7x213 7x214 7x215 7x216 0111 8 OFF 8x210 8x211 8x212 8x213 8x214 8x215 8x216 1000 9 OFF 9x210 9x211 9x212 9x213 9x214 9x215 9x216 1001 10 OFF 10x210 10x211 10x212 10x213 10x214 10x215 10x216 1010 11 OFF 11x210 11x211 11x2...

Page 130: ...103 250x103 500x103 1x106 0101 6 6x103 12x103 30x103 60x103 120x103 300x103 600x103 1 2x106 0110 7 7x103 14x103 35x103 70x103 140x103 350x103 700x103 1 4x106 0111 8 8x103 16x103 40x103 80x103 160x103 400x103 800x103 1 6x106 1000 9 9x103 18x103 45x103 90x103 180x103 450x103 900x103 1 8x106 1001 10 10 x103 20x103 50x103 100x103 200x103 500x103 1x106 2x106 1010 11 11 x103 22x103 55x103 110x103 220x10...

Page 131: ...ng CR 2 0 to 000 has no effect but counts for the write once condition Writing WCOP to 0 has no effect but counts for the write once condition When a non zero value is loaded from Flash to CR 2 0 the COP time out period is started A change of the COPOSCSEL0 or COPOSCSEL1 bit writing a different value or loosing UPOSC status while COPOSCSEL1 is clear and COPOSCSEL0 is set re starts the COP time out...

Page 132: ...2 0 bits while writing the CPMUCOP register It is intended for BDM writing the RSBCK without changing the content of WCOP and CR 2 0 0 Write of WCOP and CR 2 0 has an effect with this write of CPMUCOP 1 Write of WCOP and CR 2 0 has no effect with this write of CPMUCOP Does not count for write once 2 0 CR 2 0 COP Watchdog Timer Rate Select These bits select the COP time out rate see Table 4 14 and ...

Page 133: ...VRP Family Reference Manual Rev 1 3 NXP Semiconductors 133 Table 4 15 COP Watchdog Rates if COPOSCSEL1 1 CR2 CR1 CR0 COPCLK Cycles to time out COPCLK is ACLK divided by 2 0 0 0 COP disabled 0 0 1 2 7 0 1 0 2 9 0 1 1 2 11 1 0 0 2 13 1 0 1 2 15 1 1 0 2 16 1 1 1 2 17 ...

Page 134: ...ime Write Only in Special Mode 4 3 2 11 Reserved Register CPMUTEST1 NOTE This reserved register is designed for factory test purposes only and is not intended for general user access Writing to this register when in Special Mode can alter the S12CPMU_UHV_V8 s functionality Read Anytime Write Only in Special Mode 0x003D 7 6 5 4 3 2 1 0 R 0 0 0 0 0 0 0 0 W Reset 0 0 0 0 0 0 0 0 Unimplemented or Rese...

Page 135: ...ior to COP end of time out period to avoid a COP reset Sequences of 55 writes are allowed When the WCOP bit is set 55 and AA writes must be done in the last 25 of the selected time out period writing any value in the first 75 of the selected period will cause a COP reset 4 3 2 13 High Temperature Control Register CPMUHTCTL The CPMUHTCTL register configures the temperature sense features Read Anyti...

Page 136: ...voltage VBG can be accessed internally 3 HTE High Temperature Sensor Bandgap Voltage Enable Bit This bit enables the high temperature sensor and bandgap voltage amplifier 0 The temperature sensor and bandgap voltage amplifier is disabled 1 The temperature sensor and bandgap voltage amplifier is enabled 2 HTDS High Temperature Detect Status Bit This read only status bit reflects the temperature sta...

Page 137: ... Figure 4 18 Low Voltage Control Register CPMULVCTL Table 4 17 CPMULVCTL Field Descriptions Field Description 2 LVDS Low Voltage Detect Status Bit This read only status bit reflects the voltage level on VDDA Writes have no effect 0 Input voltage VDDA is above level VLVID or RPM 1 Input voltage VDDA is below level VLVIA and FPM 1 LVIE Low Voltage Interrupt Enable Bit 0 Interrupt request is disabled...

Page 138: ...rnal pin API_EXTCLK periodic high pulses are visible at the end of every selected period with the size of half of the minimum period APIR 0x0000 in Table 4 22 1 If APIEA and APIFE are set at the external pin API_EXTCLK a clock is visible with 2 times the selected API Period 3 APIEA Autonomous Periodical Interrupt External Access Enable Bit If set the waveform selected by bit APIES can be accessed ...

Page 139: ...t and Power Management Unit S12CPMU_UHV_V8 MC9S12VRP Family Reference Manual Rev 1 3 NXP Semiconductors 139 Figure 4 20 Waveform selected on API_EXTCLK pin APIEA 1 APIFE 1 APIES 0 APIES 1 API period API min period 2 ...

Page 140: ... ACLKTR3 ACLKTR2 ACLKTR1 ACLKTR0 0 0 W Reset F F F F F F 0 0 After de assert of System Reset a value is automatically loaded from the Flash memory Figure 4 21 Autonomous Clock Trimming Register CPMUACLKTR Table 4 19 CPMUACLKTR Field Descriptions Field Description 7 2 ACLKTR 5 0 Autonomous Clock Period Trimming Bits See Table 4 20 for trimming effects The ACLKTR 5 0 value represents a signed number...

Page 141: ...e out period of the API will show a latency time between two to three fACLK cycles due to synchronous clock gate release when the API feature gets enabled APIFE bit set 0x02F4 7 6 5 4 3 2 1 0 R APIR15 APIR14 APIR13 APIR12 APIR11 APIR10 APIR9 APIR8 W Reset 0 0 0 0 0 0 0 0 Unimplemented or Reserved Figure 4 22 Autonomous Periodical Interrupt Rate High Register CPMUAPIRH 0x02F5 7 6 5 4 3 2 1 0 R APIR...

Page 142: ... 2 ms1 1 When fACLK is trimmed to 20kHz 0 0001 0 4 ms1 0 0002 0 6 ms1 0 0003 0 8 ms1 0 0004 1 0 ms1 0 0005 1 2 ms1 0 0 FFFD 13106 8 ms1 0 FFFE 13107 0 ms1 0 FFFF 13107 2 ms1 1 0000 2 Bus Clock period 1 0001 4 Bus Clock period 1 0002 6 Bus Clock period 1 0003 8 Bus Clock period 1 0004 10 Bus Clock period 1 0005 12 Bus Clock period 1 1 FFFD 131068 Bus Clock period 1 FFFE 131070 Bus Clock period 1 FF...

Page 143: ...s reserved register is designed for factory test purposes only and is not intended for general user access Writing to this register when in Special Mode can alter the S12CPMU_UHV_V8 s functionality Read Anytime Write Only in Special Mode 0x02F6 7 6 5 4 3 2 1 0 R 0 0 0 0 0 0 0 0 W Reset 0 0 0 0 0 0 0 0 Unimplemented or Reserved Figure 4 24 Reserved Register CPMUTEST3 ...

Page 144: ...pecification for details Unimplemented or Reserved Figure 4 25 High Temperature Trimming Register CPMUHTTR Table 4 24 CPMUHTTR Field Descriptions Field Description 7 HTOE High Temperature Offset Enable Bit If set the temperature sense offset is enabled 0 The temperature sense offset is disabled HTTR 3 0 bits don t care 1 The temperature sense offset is enabled HTTR 3 0 select the temperature offse...

Page 145: ...MUIRCTRIMH L Field Descriptions Field Description 15 11 TCTRIM 4 0 IRC1M temperature coefficient Trim Bits Trim bits for the Temperature Coefficient TC of the IRC1M frequency Table 4 27 shows the influence of the bits TCTRIM 4 0 on the relationship between frequency and temperature Figure 4 29 shows an approximate TC variation relative to the nominal TC of the IRC1M i e for TCTRIM 4 0 0x00000 or 0...

Page 146: ... Management Unit S12CPMU_UHV_V8 MC9S12VRP Family Reference Manual Rev 1 3 146 NXP Semiconductors Figure 4 28 IRC1M Frequency Trimming Diagram IRCTRIM 9 0 000 IRCTRIM 9 6 IRCTRIM 5 0 IRC1M frequency IRCCLK 600KHz 1 5MHz 1MHz 3FF ...

Page 147: ...rection positive or negative of the variation of the TC relative to the nominal TC Setting TCTRIM 4 0 at 0x00000 or 0x10000 does not mean that the temperature coefficient will be zero These two combinations basically switch off the TC compensation module which results in the nominal TC of the IRC1M frequency temperature TCTRIM 4 0 0x11111 TCTRIM 4 0 0x01111 40C 150C TCTRIM 4 0 0x10000 or 0x00000 n...

Page 148: ...Indicative relative TC variation IRC1M indicative frequency drift for relative TC variation 00000 0 nominal TC of the IRC 0 00001 0 27 0 5 00010 0 54 0 9 00011 0 81 1 3 00100 1 08 1 7 00101 1 35 2 0 00110 1 63 2 2 00111 1 9 2 5 01000 2 20 3 0 01001 2 47 3 4 01010 2 77 3 9 01011 3 04 4 3 01100 3 33 4 7 01101 3 6 5 1 01110 3 91 5 6 01111 4 18 5 9 10000 0 nominal TC of the IRC 0 10001 0 27 0 5 10010 ...

Page 149: ...le Bit This bit enables the external oscillator XOSCLCP The UPOSC status bit in the CPMUFLG register indicates when the oscillation is stable and OSCCLK can be selected as source of the Bus Clock or source of the COP or RTI If the oscillator clock monitor reset is enabled OMRE 1 in CPMUOSC2 register then a loss of oscillation will lead to an oscillator clock monitor reset 0 External oscillator is ...

Page 150: ...e 0x02FB 7 6 5 4 3 2 1 0 R 0 0 0 0 0 0 0 PROT W Reset 0 0 0 0 0 0 0 0 Figure 4 31 S12CPMU_UHV_V8 Protection Register CPMUPROT Field Description PROT Clock Configuration Registers Protection Bit This bit protects the clock configuration registers from accidental overwrite see list of protected registers above Writing 0x26 to the CPMUPROT register clears the PROT bit other write accesses set the PRO...

Page 151: ...time Write Only in Special Mode 4 3 2 24 S12CPMU_UHV_V8 Oscillator Register 2 CPMUOSC2 This registers configures the external oscillator XOSCLCP Read Anytime Write Anytime if PROT 0 CPMUPROT register PLLSEL 1 CPMUCLKS register and OSCE 0 OSCCLK Enable Bit in CPMUOSC register Else write has no effect 0x02FC 7 6 5 4 3 2 1 0 R 0 0 0 0 0 0 0 0 W Reset 0 0 0 0 0 0 0 0 Unimplemented or Reserved Figure 4...

Page 152: ... Field Description 1 OMRE This bit enables the oscillator clock monitor reset 0 Oscillator clock monitor reset is disabled 1 Oscillator clock monitor reset is enabled 0 OSCMOD 0 External oscillator configured for loop controlled mode reduced amplitude on EXTAL and XTAL 1 External oscillator configured for full swing mode full swing amplitude on EXTAL and XTAL ...

Page 153: ...6 to generate the reference frequency REFCLK using the REFDIV 3 0 bits Based on the SYNDIV 5 0 bits the PLL generates the VCOCLK by multiplying the reference clock by a 2 4 6 126 128 Based on the POSTDIV 4 0 bits the VCOCLK can be divided in a range of 1 2 3 4 5 6 to 32 to generate the PLLCLK NOTE Although it is possible to set the dividers to command a very high clock frequency do not exceed the ...

Page 154: ...etector compares the frequencies of the FBCLK and the REFCLK Therefore the speed of the lock detector is directly proportional to the reference clock frequency The circuit determines the lock condition based on this comparison If PLL LOCK interrupt requests are enabled the software can wait for an interrupt request and for instance check the LOCK bit If interrupt requests are disabled software can...

Page 155: ...artup of clock system after Reset System PLLCLK Reset fVCORST CPU reset state vector fetch program execution LOCK POSTDIV 03 default target fPLL fVCO 4 12 5MHz fPLL increasing fPLL 12 5MHz tlock SYNDIV 18 default target fVCO 50MHz 00 fPLL 50MHz example change of POSTDIV RESET Pin 768 cycles startup fVCORST nSTARTUP cycles fBUS 512 cycles fVCORST 256 cycles fVCORST Core Clock Bus Clock fBUS increas...

Page 156: ...e an additional significant latency time until COP is active again after exit from Stop Mode due to clock domain crossing synchronization This latency time occurs if COP clock source is ACLK and the CSAD bit is set please refer to CSAD bit description for details 4 4 4 Full Stop Mode using Oscillator Clock as source of the Bus Clock An example of what happens going into Full Stop Mode and exiting ...

Page 157: ...OP is active again after exit from Stop Mode due to clock domain crossing synchronization This latency time occurs if COP clock source is ACLK and the CSAD bit is set please refer to CSAD bit description for details CPU UPOSC tlock STOP instruction execution interrupt continue execution wake up tSTP_REC Core Clock select OSCCLK as Core Bus Clock by writing PLLSEL to 0 PLLSEL automatically set when...

Page 158: ... how to use the oscillator as source of the Bus Clock is shown in Figure 4 37 Figure 4 37 Enabling the external oscillator PLLSEL OSCE OSCCLK Core enable external oscillator by writing OSCE bit to one crystal resonator starts oscillating UPOSC UPOSC flag is set upon successful start of oscillation select OSCCLK as Core Bus Clock by writing PLLSEL to zero Clock based on PLL Clock based on OSCCLK tU...

Page 159: ... clock for the PLL is based on the external oscillator The clock sources for COP and RTI can be based on the internal reference clock generator or on the external oscillator clock or the RC Oscillator ACLK This mode can be entered from default mode PEI by performing the following steps 1 Configure the PLL for desired bus frequency 2 Enable the external Oscillator OSCE bit 3 Wait for oscillator to ...

Page 160: ...LSEL 0 Loosing PLL lock status LOCK 0 means loosing the oscillator status information as well UPOSC 0 The impact of loosing the oscillator status UPOSC 0 in PBE mode is as follows PLLSEL is set automatically and the Bus clock is switched back to the PLL clock The PLLCLK is derived from the VCO clock with its actual frequency divided by four until the PLL locks again NOTEApplication software needs ...

Page 161: ...2 shows which vector will be fetched NOTE While System Reset is asserted the PLLCLK runs with the frequency fVCORST PLL Clock Monitor Reset None Oscillator Clock Monitor Reset OSCE 1 in CPMUOSC register and OMRE 1 in CPMUOSC2 register COP Reset CR 2 0 in CPMUCOP register Table 4 32 Reset Vector Selection Sampled RESET Pin 256 cycles after release Oscillator monitor fail pending COP time out pendin...

Page 162: ...lator and the oscillator clock monitor are disabled 4 5 4 PLL Clock Monitor Reset In case of loss of PLL clock oscillation or the PLL clock frequency is below the failure assert frequency fPMFA see device electrical characteristics for values the S12CPMU_UHV_V8 generates a PLL Clock Monitor Reset In Full Stop Mode the PLL and the PLL clock monitor are disabled 4 5 4 1 Computer Operating Properly W...

Page 163: ...d by setting WCOP in the CPMUCOP register In this mode writes to the CPMUARMCOP register to clear the COP timer must occur in the last 25 of the selected time out period A premature write will immediately reset the part In MCU Normal Mode the COP time out period CR 2 0 and COP window WCOP setting can be automatically pre loaded at reset release from NVM memory if values are defined in the NVM by t...

Page 164: ...rnal supply VDD drops below an appropriate voltage level The POR is deasserted if the internal supply VDD exceeds an appropriate voltage level voltage levels not specified in this document because this internal supply is not visible on device pins 4 5 6 Low Voltage Reset LVR The on chip LVR circuitry detects when one of the supply voltages VDD VDDX and VDDF drops below an appropriate voltage level...

Page 165: ...e LOCKIE bit to zero The PLL Lock interrupt flag LOCKIF is set to1 when the lock condition has changed and is cleared to 0 by writing a 1 to the LOCKIF bit 4 6 1 3 Oscillator Status Interrupt When the OSCE bit is 0 then UPOSC stays 0 When OSCE 1 the UPOSC bit is set after the LOCK bit is set Upon detection of a status change UPOSC the OSCIF flag is set Going into Full Stop Mode or disabling the os...

Page 166: ...interrupt indicated by flag APIF 1 is triggered if interrupt enable bit APIE 1 The timer is re started automatically again after it has set APIF The procedure to change APICLK or APIR 15 0 is first to clear APIFE then write to APICLK or APIR 15 0 and afterwards set APIFE The API Trimming bits ACLKTR 5 0 must be set so the minimum period equals 0 2 ms if stable frequency is desired See Table 4 20 f...

Page 167: ...tation using the same clock source for both COP and API The Interrupt Service Routine ISR of the Autonomous Periodic Interrupt API should contain the write instruction to the CPMUARMCOP register The value byte written is derived from the main routine alternating sequence of 55 and AA of the application software Using this method then in the case of a runtime or program sequencing issue the applica...

Page 168: ...S12 Clock Reset and Power Management Unit S12CPMU_UHV_V8 MC9S12VRP Family Reference Manual Rev 1 3 168 NXP Semiconductors ...

Page 169: ...mpatible to the BDM of the S12 family with the following exceptions TAGGO command not supported by S12SBDM External instruction tagging feature is part of the DBG module S12SBDM register map and register content modified Family ID readable from BDM ROM at global address 0x3_FF0F in active BDM value for devices with HCS12S core is 0xC2 Clock switch removed from BDM CLKSW bit removed from BDMSTS reg...

Page 170: ...un mode and not being secured The BDM does not provide controls to conserve power during run mode Normal modes General operation of the BDM is available and operates the same in all normal modes Special single chip mode In special single chip mode background operation is enabled and active out of reset This allows programming a system with blank memory 5 1 2 2 Secure Mode Operation If the device i...

Page 171: ...n for the background debug mode The communication rate of this pin is always the BDM clock frequency defined at device level refer to device overview section When modifying the VCO clock please make sure that the communication rate is adapted accordingly and a communication time out BDM soft reset has occurred 5 3 Memory Map and Register Definition 5 3 1 Module Memory Map Table 5 2 shows the BDM m...

Page 172: ...3_FF0F Family ID part of BDM firmware ROM 1 0x3_FF10 0x3_FFFF BDM firmware ROM 240 Global Address Register Name Bit 7 6 5 4 3 2 1 Bit 0 0x3_FF00 Reserved R X X X X X X 0 0 W 0x3_FF01 BDMSTS R ENBDM BDMACT 0 SDV TRACE 0 UNSEC 0 W 0x3_FF02 Reserved R X X X X X X X X W 0x3_FF03 Reserved R X X X X X X X X W 0x3_FF04 Reserved R X X X X X X X X W 0x3_FF05 Reserved R X X X X X X X X W 0x3_FF06 BDMCCR R C...

Page 173: ...ved R 0 0 0 0 0 0 0 0 W Register Global Address 0x3_FF01 7 6 5 4 3 2 1 0 R ENBDM BDMACT 0 SDV TRACE 0 UNSEC 0 W Reset Special Single Chip Mode 01 1 ENBDM is read as 1 by a debugging environment in special single chip mode when the device is not secured or secured but fully erased Flash This is because the ENBDM bit is set by the standard BDM firmware before a BDM command can be fully transmitted a...

Page 174: ...e command It is cleared when the next BDM command has been received or BDM is exited SDV is used by the standard BDM firmware to control program flow execution 0 Data phase of command not complete 1 Data phase of command is complete 3 TRACE TRACE1 BDM Firmware Command is Being Executed This bit gets set when a BDM TRACE1 firmware command is first recognized It will stay set until BDM firmware is e...

Page 175: ...egister BDMPPR Figure 5 5 BDM Program Page Register BDMPPR Read All modes through BDM operation when not secured Write All modes through BDM operation when not secured Register Global Address 0x3_FF06 7 6 5 4 3 2 1 0 R CCR7 CCR6 CCR5 CCR4 CCR3 CCR2 CCR1 CCR0 W Reset Special Single Chip Mode 1 1 0 0 1 0 0 0 All Other Modes 0 0 0 0 0 0 0 0 Register Global Address 0x3_FF08 7 6 5 4 3 2 1 0 R BPAE 0 0 ...

Page 176: ... into special single chip mode with the system secured a secured mode BDM firmware lookup table is brought into the map overlapping a portion of the standard BDM firmware lookup table The secure BDM firmware verifies that the on chip Flash EEPROM are erased This being the case the UNSEC and ENBDM bit will get set The BDM program jumps to the start of the standard BDM firmware and the secured mode ...

Page 177: ... such a case the PC must be set to the next valid address via a WRITE_PC command before executing the GO command 5 4 3 BDM Hardware Commands Hardware commands are used to read and write target system memory locations and to enter active background debug mode Target system memory includes all memory that is accessible by the CPU such as on chip RAM Flash I O and control registers Hardware commands ...

Page 178: ...se after the command is executed ACK_DISABLE D6 None Disable Handshake This command does not issue an ACK pulse READ_BD_BYTE E4 16 bit address 16 bit data out Read from memory with standard BDM firmware lookup table in map Odd address data on low byte even address data on high byte READ_BD_WORD EC 16 bit address 16 bit data out Read from memory with standard BDM firmware lookup table in map Must b...

Page 179: ...t Read D accumulator READ_X 65 16 bit data out Read X index register READ_Y 66 16 bit data out Read Y index register READ_SP 67 16 bit data out Read stack pointer WRITE_NEXT2 42 16 bit data in Increment X index register by 2 X X 2 then write word to location pointed to by X WRITE_PC 43 16 bit data in Write program counter WRITE_D 44 16 bit data in Write D accumulator WRITE_X 45 16 bit data in Writ...

Page 180: ...lable in the BDM shift register ready to be shifted out For BDM firmware write commands the external host must wait 36 bus clock cycles after sending the data to be written before attempting to send a new command This is to avoid disturbing the BDM shift register before the write has been completed The external host should wait for at least for 76 bus clock cycles after a TRACE1 or GO command befo...

Page 181: ...ive pull up that is enabled at all times It is assumed that there is an external pull up and that drivers connected to BKGD do not typically drive the high level Since R C rise time could be unacceptably long the target system and host provide brief driven high speedup pulses to drive BKGD to a logic 1 The source of this speedup pulse is the host for transmit cases and the target for receive cases...

Page 182: ...ost drives the high speedup pulses in these two cases the rising edges look like digitally driven signals Figure 5 7 BDM Host to Target Serial Bit Timing The receive cases are more complicated Figure 5 8 shows the host receiving a logic 1 from the target system Since the host is asynchronous to the target there is up to one clock cycle delay from the host generated falling edge on BKGD to the perc...

Page 183: ...ogic 0 it drives the BKGD pin low for 13 target clock cycles then briefly drives it high to speed up the rising edge The host samples the bit level about 10 target clock cycles after starting the bit time Figure 5 9 BDM Target to Host Serial Bit Timing Logic 0 High Impedance Earliest Start of Next Bit R C Rise 10 Cycles 10 Cycles Host Samples BKGD Pin Perceived Start of Bit Time BKGD Pin BDM Clock...

Page 184: ...it retrieval if the last issued command was a read command or start a new command if the last command was a write command or a control command BACKGROUND GO GO_UNTIL or TRACE1 The ACK pulse is not issued earlier than 32 serial clock cycles after the BDM command was issued The end of the BDM command is assumed to be the 16th tick of the last bit This minimum delay assures enough time for the host t...

Page 185: ...st should follow this timing constraint in order to avoid the risk of an electrical conflict in the BKGD pin NOTE The only place the BKGD pin can have an electrical conflict is when one side is driving low and the other side is issuing a speedup pulse high Other highs are pulled rather than driven However at low rates the time of the speedup pulse can become lengthy and so the potential conflict t...

Page 186: ...at is issued and on the selected bus clock rate When the SYNC command starts during this latency time the READ or WRITE command will not be aborted but the corresponding ACK pulse will be aborted A pending GO TRACE1 or GO_UNTIL command can not be aborted Only the corresponding ACK pulse can be aborted by the SYNC command Although it is not recommended the host could abort a pending BDM command by ...

Page 187: ...and the SYNC request pulse This conflict could occur if a POD device is connected to the target BKGD pin and the target is already in debug active mode Consider that the target CPU is executing a pending BDM command at the exact moment the POD is being connected to the BKGD pin In this case an ACK pulse is issued along with the SYNC command In this case there is an electrical conflict between the ...

Page 188: ...irmware Commands for more information on the BDM commands The ACK_ENABLE sends an ACK pulse when the command has been completed This feature could be used by the host to evaluate if the target supports the hardware handshake protocol If an ACK pulse is issued in response to this command the host knows that the target supports the hardware handshake protocol If the target does not support the hardw...

Page 189: ... BKGD pin so it reverts to high impedance The host measures the low time of this 128 cycle SYNC response pulse and determines the correct speed for subsequent BDM communications Typically the host can determine the correct communication speed within a few percent of the actual target speed and the communication protocol can easily tolerate speed errors of several percent As soon as the SYNC reques...

Page 190: ...when tracing a stop or wait instruction Hence there is no ACK pulse when BDM active mode is entered as part of the TRACE1 command after CPU exited from stop or wait mode All valid commands sent during CPU being in stop or wait mode or after CPU exited from stop or wait mode will have an ACK pulse The handshake feature becomes disabled only when system stop mode has been reached Hence after a syste...

Page 191: ...sued After that period the read command is discarded and the data is no longer available for retrieval Any negative edge in the BKGD pin after the time out period is considered to be a new command or a SYNC request Note that whenever a partially issued command or partially retrieved data has occurred the time out in the serial communication is active This means that if a time frame higher than 512...

Page 192: ...Background Debug Module S12SBDMV1 MC9S12VRP Family Reference Manual Rev 1 3 192 NXP Semiconductors ...

Page 193: ...er program which is then monitored by the S12DBGV2 module Alternatively the S12DBGV2 module can be configured over a serial interface using SWI routines 6 1 1 Glossary Of Terms COF Change Of Flow Change in the program flow due to a conditional branch indexed jump or interrupt BDM Background Debug Mode S12SBDM Background Debug Module DUG Device User Guide describing the features of the device into ...

Page 194: ...mask register Comparators B and C compare the full address bus only Each comparator features selection of read or write access cycles Comparator B allows selection of byte or word access cycles Comparator matches can initiate state sequencer transitions Three comparator modes Simple address data comparator match mode Inside address range mode Addmin Address Addmax Outside address range match mode ...

Page 195: ...The DBG module tracing is disabled if the MCU is secure however breakpoints can still be generated 6 1 5 Block Diagram Figure 6 1 Debug Module Block Diagram Table 6 2 Mode Dependent Restriction Summary BDM Enable BDM Active MCU Secure Comparator Matches Enabled Breakpoints Possible Tagging Possible Tracing Possible x x 1 Yes Yes Yes No 0 0 0 Yes Only SWI Yes Yes 0 1 0 Active BDM not possible when ...

Page 196: ... DBGSR R 1 TBF 0 0 0 0 SSF2 SSF1 SSF0 W 0x0022 DBGTCR R 0 TSOURCE 0 0 TRCMOD 0 TALIGN W 0x0023 DBGC2 R 0 0 0 0 0 0 ABCM W 0x0024 DBGTBH R Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 W 0x0025 DBGTBL R Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 W 0x0026 DBGCNT R 1 TBF 0 CNT W 0x0027 DBGSCRX R 0 0 0 0 SC3 SC2 SC1 SC0 W 0x0027 DBGMFR R 0 0 0 0 0 MC2 MC1 MC0 W 2 0x0028 DBGACTL R SZE SZ T...

Page 197: ...3 are not affected by the write since up until the write operation ARM 1 preventing these bits from being written These bits must be cleared using a second write if required 0x002C DBGADH R Bit 15 14 13 12 11 10 9 Bit 8 W 0x002D DBGADL R Bit 7 6 5 4 3 2 1 Bit 0 W 0x002E DBGADHM R Bit 15 14 13 12 11 10 9 Bit 8 W 0x002F DBGADLM R Bit 7 6 5 4 3 2 1 Bit 0 W 1 This bit is visible at DBGCNT 7 and DBGSR ...

Page 198: ... by setting TRIG and ARM simultaneously 0 Do not trigger until the state sequencer enters the Final State 1 Trigger immediately 4 BDM Background Debug Mode Enable This bit determines if a breakpoint causes the system to enter Background Debug Mode BDM or initiate a Software Interrupt SWI If this bit is set but the BDM is not enabled by the ENBDM bit in the BDM module then breakpoints default to SW...

Page 199: ...stem generated resets have no affect on this bit This bit is also visible at DBGCNT 7 2 0 SSF 2 0 State Sequencer Flag Bits The SSF bits indicate in which state the State Sequencer is currently in During a debug session on each transition to a new state these bits are updated If the debug session is ended by software clearing the ARM bit then these bits retain their value to reflect the last state...

Page 200: ...o read the trace buffer 0 Debug session without tracing requested 1 Debug session with tracing requested 3 2 TRCMOD Trace Mode Bits See Section 6 4 5 2 Trace Modes for detailed Trace Mode descriptions In Normal Mode change of flow information is stored In Loop1 Mode change of flow information is stored but redundant entries into trace memory are inhibited In Detail Mode address and data for all me...

Page 201: ...ug Control Register2 DBGC2 Table 6 9 DBGC2 Field Descriptions Field Description 1 0 ABCM 1 0 A and B Comparator Match Control These bits determine the A and B comparator match mapping as described in Table 6 10 Table 6 10 ABCM Encoding ABCM Description 00 Match0 mapped to comparator A match Match1 mapped to comparator B match 01 Match 0 mapped to comparator A B inside range Match1 disabled 10 Matc...

Page 202: ...o be read When the ARM bit is set the trace buffer is locked to prevent reading The trace buffer can only be unlocked for reading by writing to DBGTB with an aligned word write when the module is disarmed The DBGTB register can be read only as an aligned word any byte reads or misaligned access of these registers return 0 and do not cause the trace buffer pointer to increment to the next trace buf...

Page 203: ...lines stored in the Trace Buffer Table 6 13 shows the correlation between the CNT bits and the number of valid data lines in the Trace Buffer When the CNT rolls over to zero the TBF bit in DBGSR is set and incrementing of CNT will continue in end trigger mode The DBGCNT register is cleared when ARM in DBGC1 is written to a one The DBGCNT register is cleared by power on reset initialization but is ...

Page 204: ...comparator matches or tag hits and defines the next state for the state sequencer following a match The three debug state control registers are located at the same address in the register address map 0x0027 Each register can be accessed using the COMRV bits in DBGC1 to blend in the required register The COMRV 11 value blends in the match flag register DBGMFR Table 6 14 State Control Register Acces...

Page 205: ...lowed by the match on the lower channel number 0 1 2 Thus with SC 3 0 1101 a simultaneous match0 match1 transitions to final state Address 0x0027 7 6 5 4 3 2 1 0 R 0 0 0 0 SC3 SC2 SC1 SC0 W Reset 0 0 0 0 0 0 0 0 Unimplemented or Reserved Figure 6 9 Debug State Control Register 1 DBGSCR1 Table 6 15 DBGSCR1 Field Descriptions Field Description 3 0 SC 3 0 These bits select the targeted next state whi...

Page 206: ...rity followed by the match on the lower channel number 0 1 2 Address 0x0027 7 6 5 4 3 2 1 0 R 0 0 0 0 SC3 SC2 SC1 SC0 W Reset 0 0 0 0 0 0 0 0 Unimplemented or Reserved Figure 6 10 Debug State Control Register 2 DBGSCR2 Table 6 17 DBGSCR2 Field Descriptions Field Description 3 0 SC 3 0 These bits select the targeted next state whilst in State2 based upon the match event Table 6 18 State2 Sequencer ...

Page 207: ...ed by the match on the lower channel number 0 1 2 Address 0x0027 7 6 5 4 3 2 1 0 R 0 0 0 0 SC3 SC2 SC1 SC0 W Reset 0 0 0 0 0 0 0 0 Unimplemented or Reserved Figure 6 11 Debug State Control Register 3 DBGSCR3 Table 6 19 DBGSCR3 Field Descriptions Field Description 3 0 SC 3 0 These bits select the targeted next state whilst in State3 based upon the match event Table 6 20 State3 Sequencer Next State ...

Page 208: ...mparator B consists of four register bytes three address bus compare registers and a control register Comparator C consists of four register bytes three address bus compare registers and a control register Each set of comparator registers can be accessed using the COMRV bits in the DBGC1 register Unimplemented registers e g Comparator B data bus and data bus masking read as zero and cannot be writ...

Page 209: ... Comparator B Address 0x0028 7 6 5 4 3 2 1 0 R 0 0 TAG BRK RW RWE 0 COMPE W Reset 0 0 0 0 0 0 0 0 Unimplemented or Reserved Figure 6 15 Debug Comparator Control Register DBGCCTL Comparator C Table 6 22 DBGXCTL Field Descriptions Field Description 7 SZE Comparators A and B Size Comparator Enable Bit The SZE bit controls whether access size comparison is enabled for the associated comparator This bi...

Page 210: ...if active is terminated and the module disarmed 3 RW Read Write Comparator Value Bit The RW bit controls whether read or write is used in compare for the associated comparator The RW bit is not used if RWE 0 This bit is ignored if the TAG bit in the same register is set 0 Write cycle is matched1Read cycle is matched 2 RWE Read Write Enable Bit The RWE bit controls whether read or write comparison ...

Page 211: ... armed See Table 6 24 for visible register encoding Address 0x0029 7 6 5 4 3 2 1 0 R 0 0 0 0 0 0 Bit 17 Bit 16 W Reset 0 0 0 0 0 0 0 0 Unimplemented or Reserved Figure 6 16 Debug Comparator Address High Register DBGXAH COMRV Visible Comparator 00 DBGAAH DBGAAM DBGAAL 01 DBGBAH DBGBAM DBGBAL 10 DBGCAH DBGCAM DBGCAL 11 None Table 6 25 DBGXAH Field Descriptions Field Description 1 0 Bit 17 16 Compara...

Page 212: ...o a logic one or logic zero 0 Compare corresponding address bit to a logic zero 1 Compare corresponding address bit to a logic one Address 0x002B 7 6 5 4 3 2 1 0 R Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 W Reset 0 0 0 0 0 0 0 0 Figure 6 18 Debug Comparator Address Low Register DBGXAL Table 6 27 DBGXAL Field Descriptions Field Description 7 0 Bits 7 0 Comparator Address Low Compare Bits The...

Page 213: ...ar 0 Compare corresponding data bit to a logic zero 1 Compare corresponding data bit to a logic one Address 0x002D 7 6 5 4 3 2 1 0 R Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 W Reset 0 0 0 0 0 0 0 0 Figure 6 20 Debug Comparator Data Low Register DBGADL Table 6 29 DBGADL Field Descriptions Field Description 7 0 Bits 7 0 Comparator Data Low Compare Bits The Comparator data low compare bits con...

Page 214: ...son A match with a comparator register value can initiate a state sequencer transition to another state see Figure 6 24 Either forced or tagged matches are possible Using Table 6 30 DBGADHM Field Descriptions Field Description 7 0 Bits 15 8 Comparator Data High Mask Bits The Comparator data high mask bits control whether the selected comparator compares the data bus bits 15 8 to the corresponding ...

Page 215: ...omparator A also compares the data buses to the data stored in DBGADH DBGADL and allows masking of individual data bus bits All comparators are disabled in BDM and during BDM accesses The comparator match control logic see Figure 6 23 configures comparators to monitor the buses for an exact address or an address range whereby either an access inside or outside the specified range generates a match...

Page 216: ...ator match has occurred the condition that caused the original match is not verified again on subsequent matches Thus if a particular data value is verified at a given address this address may not still contain that data value when a subsequent match occurs Match 0 1 2 map directly to Comparators A B C respectively except in range modes see Section 6 3 2 4 Debug Control Register2 DBGC2 Comparator ...

Page 217: ... in Table 6 32 Table 6 34 Comparator A Matches When Accessing ADDR n Table 6 33 Comparator B Access Size Considerations Condition For Valid Match Comp B Address RWE SZE SZ8 Examples Word and byte accesses of ADDR n ADDR n 1 1 A word access of ADDR n 1 also accesses ADDR n but does not generate a match The comparator address register must contain the exact address from the code 0 0 X MOVB BYTE ADDR...

Page 218: ...arison the data bus can also be used for qualification by using the comparator A data registers Furthermore the DBGACTL RW and RWE bits can be used to qualify the range comparison on either a read or a write access The corresponding DBGBCTL bits are ignored The SZE and SZ control bits are ignored in range mode The comparator A TAG bit is used to tag range comparisons The comparator B TAG bit is ig...

Page 219: ...d matching a comparator channel match can immediately initiate a transition to the next state sequencer state whereby the corresponding flags in DBGSR are set The state control register for the current state determines the next state Forced matches are typically generated 2 3 bus cycles after the final matching address bus cycle independent of comparator RWE RW settings Furthermore since opcode fe...

Page 220: ...icted Each transition updates the SSF 2 0 flags in DBGSR accordingly to indicate the current state Alternatively writing to the TRIG bit in DBGSC1 provides an immediate trigger independent of comparator matches Independent of the state sequencer each comparator channel can be individually configured to generate an immediate breakpoint when a match occurs through the use of the BRK bits in the DBGx...

Page 221: ...BGCNT is incremented Tracing of CPU activity is disabled when the BDM is active Reading the trace buffer whilst the DBG is armed returns invalid data and the trace buffer pointer is not incremented 6 4 5 1 Trace Trigger Alignment Using the TALIGN bit see Section 6 3 2 3 Debug Trace Control Register DBGTCR it is possible to align the trigger with the end or the beginning of a tracing session If end...

Page 222: ...tored in the trace buffer Stored information includes the full 18 bit address bus and information bits which contains a source destination bit to indicate whether the stored address was a source address or destination address NOTE When a COF instruction with destination address is executed the destination address is stored to the trace buffer on instruction completion indicating the COF has taken ...

Page 223: ...ctor addresses since repeated entries of these would most likely indicate a bug in the user s code that the DBG module is designed to help find 6 4 5 2 3 Detail Mode In Detail Mode address and data for all memory and register accesses is stored in the trace buffer This mode is intended to supply additional information on indexed indirect addressing modes where storing only the destination address ...

Page 224: ...the data line on each trace buffer entry In Detail mode CINF comprises of R W and size access information CRW and CSZ respectively Single byte data accesses in Detail Mode are always stored to the low byte of the trace buffer DATAL and the high byte is cleared When tracing word accesses the byte at the lower address is always stored to trace buffer byte1 and the byte at the higher address is store...

Page 225: ...2 Bit 1 Bit 0 CSD CVA PC17 PC16 Figure 6 26 Information Bits PCH Table 6 39 PCH Field Descriptions Bit Description 3 CSD Source Destination Indicator In Normal and Loop1 mode this bit indicates if the corresponding stored address is a source or destination address This bit has no meaning in Compressed Pure PC mode 0 Source Address 1 Destination Address 2 CVA Vector Indicator In Normal and Loop1 mo...

Page 226: ...t reading The trace buffer can only be unlocked for reading by a single aligned word write to DBGTB when the module is disarmed The Trace Buffer can only be read through the DBGTB register using aligned word reads any byte or misaligned reads return 0 and do not cause the trace buffer pointer to increment to the next trace buffer address The Trace Buffer data is read out first in first out By read...

Page 227: ...t valid data even if a reset occurred during the tracing session To read the trace buffer after a reset TSOURCE must be set otherwise the trace buffer reads as all zeroes Generally debugging occurrences of system resets is best handled using end trigger alignment since the reset may occur before the trace trigger which in the begin trigger alignment case means no information would be stored in the...

Page 228: ...ected by the TSOURCE bit breakpoints are requested when the tracing session has completed thus if Begin aligned triggering is selected the breakpoint is requested only on completion of the subsequent trace see Table 6 42 If no tracing session is selected breakpoints are requested immediately If the BRK bit is set then the associated breakpoint is generated immediately independent of tracing trigge...

Page 229: ...M requests over SWI requests if the breakpoint happens to coincide with a SWI instruction in user code On returning from BDM the SWI from user code gets executed BDM cannot be entered from a breakpoint unless the ENABLE bit is set in the BDM If entry to BDM via a BGND instruction is attempted and the ENABLE bit in the BDM is cleared the CPU actually executes the BDM firmware code checks the ENABLE...

Page 230: ...tate Machine scenarios Defining the state control registers as SCR1 SCR2 SCR3 and M0 M1 M2 as matches on channels 0 1 2 respectively SCR encoding supported by S12SDBGV1 are shown in black SCR encoding supported only in S12SDBGV2 are shown in red For backwards compatibility the new scenarios use a 4th bit in each SCR register Thus the existing encoding for SCRx 2 0 is not changed 6 5 2 Scenario 1 A...

Page 231: ...red for range mode Figure 6 30 Scenario 2c All 3 scenarios 2a 2b 2c are possible with the S12SDBGV1 SCR encoding 6 5 4 Scenario 3 A trigger is generated immediately when one of up to 3 given events occurs Figure 6 31 Scenario 3 Scenario 3 is possible with S12SDBGV1 SCR encoding 6 5 5 Scenario 4 Trigger if a sequence of 2 events is carried out in an incorrect order Event A must be followed by event...

Page 232: ... is that now range comparisons can be included channel0 This however violates the S12SDBGV1 specification which states that a match leading to final state always has priority in case of a simultaneous match whilst priority is also given to the lowest channel number For S12SDBG the corresponding CPU priority decoder is removed to support this such that on simultaneous taghits taghits pointing to fi...

Page 233: ...a State1 State3 transition using M0 is now possible This is advantageous because range and data bus comparisons use channel0 only Figure 6 35 Scenario 6 6 5 8 Scenario 7 Trigger when a series of 3 events is executed out of order Specifying the event order as M1 M2 M0 to run in loops 120120120 Any deviation from that order should trigger This scenario is not possible using the S12SDBGV1 SCR encodin...

Page 234: ... encoding 6 5 10 Scenario 9 Trigger when a routine event at A M2 does not follow either B or C M1 or M0 before they are executed again This cannot be realized with theS12SDBGV1 SCR encoding due to OR limitations By changing the SCR2 encoding as shown in red this scenario becomes possible Figure 6 39 Scenario 9 6 5 11 Scenario 10 Trigger if an event M0 occurs following up to two successive M2 event...

Page 235: ...reset M1 Figure 6 40 Scenario 10a Figure 6 41 Scenario 10b Scenario 10b shows the case that after M2 then M1 must occur before M0 Starting from a particular point in code event M2 must always be followed by M1 before M0 If after any M2 event M0 occurs before M1 then a trigger is generated State1 Final State State3 State2 SCR1 0010 SCR2 0100 SCR3 0010 M2 M2 M0 M1 M1 State1 Final State State3 State2...

Page 236: ...S12S Debug Module S12DBGV2 MC9S12VRP Family Reference Manual Rev 1 3 236 NXP Semiconductors ...

Page 237: ... Glossary Table 7 2 contains terms and abbreviations used in the document 7 1 2 Features Interrupt vector base register IVBR One spurious interrupt vector at address vector base1 0x0080 Version Number Revision Date Effective Date Author Description of Changes 01 02 13 Sep 2007 updates for S12P family devices re added XIRQ and IRQ references since this functionality is used on devices without D2D a...

Page 238: ...odes of Operation Run mode This is the basic mode of operation Wait mode In wait mode the clock to the INT module is disabled The INT module is however capable of waking up the CPU from wait mode if an interrupt occurs Please refer to Section 7 5 3 Wake Up from Stop or Wait Mode for details Stop Mode In stop mode the clock to the INT module is disabled The INT module is however capable of waking u...

Page 239: ...rs accessible in the INT module 7 3 1 Register Descriptions This section describes in address order all the INT registers and their individual bits 7 3 1 1 Interrupt Vector Base Register IVBR Read Anytime Write Anytime Address 0x0120 7 6 5 4 3 2 1 0 R IVB_ADDR 7 0 W Reset 1 1 1 1 1 1 1 1 Figure 7 2 Interrupt Vector Base Register IVBR Wake Up IVBR Interrupt Requests Interrupt Requests CPU Vector Ad...

Page 240: ...terrupt requests If the X bit in the CCR is cleared it is possible to interrupt an I bit maskable interrupt by an X bit maskable interrupt It is possible to nest non maskable interrupt requests for example by nesting SWI or TRAP calls Since an interrupt vector is only supplied at the time when the CPU requests it it is possible that a higher priority interrupt request could override the original i...

Page 241: ...pplicable 2 Clock monitor reset request 3 COP watchdog reset request 7 4 4 Exception Priority The priority from highest to lowest and address of all exception vectors issued by the INT module upon request by the CPU is shown in Table 7 4 Table 7 4 Exception Vector Map and Priority Vector Address1 1 16 bits vector address based Source 0xFFFE Pin reset power on reset illegal address reset low voltag...

Page 242: ... maskable interrupt requests can interrupt the current ISR An ISR of an interruptible I bit maskable interrupt request could basically look like this 1 Service interrupt that is clear interrupt flags copy data etc 2 Clear I bit in the CCR by executing the instruction CLI thus allowing other I bit maskable interrupt requests 3 Process data 4 Return from interrupt by executing the instruction RTI 7 ...

Page 243: ...ures works following the same rules like any interrupt request that is care must be taken that the X interrupt request used for wake up remains active at least until the system begins execution of the instruction following the WAI or STOP instruction otherwise wake up may not occur 1 The capability of the XIRQ pin to wake up the MCU with the X bit set may not be available if for example the XIRQ p...

Page 244: ...Interrupt Module S12SINTV1 MC9S12VRP Family Reference Manual Rev 1 3 244 NXP Semiconductors ...

Page 245: ...ffective Date Author Description of Changes V02 07 11 Feb 2011 11 Feb 2011 Connectivity Information regarding internal channel_6 added to Table 8 15 V02 08 29 Mar 2011 29 Mar 2011 Fixed typo in bit description field Table 8 14 for bits CD CC CB CA Last sentence contained a wrong highest channel number it is not AN7 to AN0 instead it is AN11 to AN0 V02 09 22 Jun 2012 22 Jun 2012 Update of register ...

Page 246: ...perature sensor 1 to 12 conversion sequence lengths Continuous conversion mode Multiple channel scans Configurable external trigger functionality on any AD channel or any of four additional trigger inputs The four additional trigger inputs can be chip external or internal Refer to device specification for availability and connectivity Configurable location for channel wrap around when converting m...

Page 247: ...ence in progress and if a sequence was aborted restarts it after exiting stop mode This has the same effect consequences as starting a conversion sequence with write to ATDCTL5 So after exiting from stop mode with a previously aborted sequence all flags are cleared etc Wait Mode ADC12B12C behaves same in Run and Wait Mode For reduced power consumption continuous conversions should be aborted befor...

Page 248: ...ive Approximation Register SAR Results ATD 0 ATD 1 ATD 2 ATD 3 ATD 4 ATD 5 ATD 6 ATD 7 and DAC Sample Hold VDDA VRL VRH Sequence Complete Comparator Clock Prescaler Bus Clock ATD Clock AN5 AN4 AN3 AN1 AN0 AN7 ETRIG0 See device specifi cation for availability ETRIG1 ETRIG2 ETRIG3 and connectivity Timing Control ATDDIEN ATDCTL1 Trigger Mux Interrupt Compare Interrupt AN2 AN8 AN9 AN10 AN11 ATD 8 ATD ...

Page 249: ... voltage VRL is the low reference voltage for ATD conversion 8 2 1 4 VDDA VSSA These pins are the power supplies for the analog circuitry of the ADC12B12C block 8 3 Memory Map and Register Definition This section provides a detailed description of all registers accessible in the ADC12B12C 8 3 1 Module Memory Map Figure 8 2 gives an overview on all ADC12B12C registers NOTE Register Address Base Add...

Page 250: ... 12 1 Left Justified Result Data DJM 0 and Section 8 3 2 12 2 Right Justified Result Data DJM 1 W 0x0016 ATDDR3 R See Section 8 3 2 12 1 Left Justified Result Data DJM 0 and Section 8 3 2 12 2 Right Justified Result Data DJM 1 W 0x0018 ATDDR4 R See Section 8 3 2 12 1 Left Justified Result Data DJM 0 and Section 8 3 2 12 2 Right Justified Result Data DJM 1 W 0x001A ATDDR5 R See Section 8 3 2 12 1 L...

Page 251: ...ied Result Data DJM 0 and Section 8 3 2 12 2 Right Justified Result Data DJM 1 W 0x0026 ATDDR11 R See Section 8 3 2 12 1 Left Justified Result Data DJM 0 and Section 8 3 2 12 2 Right Justified Result Data DJM 1 W 0x0028 0x002F Unimple mented R 0 0 0 0 0 0 0 0 W Address Name Bit 7 6 5 4 3 2 1 Bit 0 Unimplemented or Reserved Figure 8 2 ADC12B12C Register Summary Sheet 3 of 3 ...

Page 252: ...AP3 WRAP2 WRAP1 WRAP0 W Reset 0 0 0 0 1 1 1 1 Unimplemented or Reserved Figure 8 3 ATD Control Register 0 ATDCTL0 Table 8 1 ATDCTL0 Field Descriptions Field Description 3 0 WRAP 3 0 Wrap Around Channel Select Bits These bits determine the channel for wrap around when doing multi channel conversions The coding is summarized in Table 8 2 Table 8 2 Multi Channel Wrap Around Coding WRAP3 WRAP2 WRAP1 W...

Page 253: ...ular ETRIG3 0 input option is not available writing a 1 to ETRISEL only sets the bit but has no effect this means that one of the AD channels selected by ETRIGCH3 0 is configured as the source for external trigger The coding is summarized in Table 8 5 6 5 SRES 1 0 A D Resolution Select These bits select the resolution of A D conversion results See Table 8 4 for coding 4 SMP_DIS Discharge Before Sa...

Page 254: ...AN4 0 0 1 0 1 AN5 0 0 1 1 0 AN6 0 0 1 1 1 AN7 0 1 0 0 0 AN8 0 1 0 0 1 AN9 0 1 0 1 0 AN10 0 1 0 1 1 AN11 0 1 1 0 0 AN11 0 1 1 0 1 AN11 0 1 1 1 0 AN11 0 1 1 1 1 AN11 1 0 0 0 0 ETRIG01 1 Only if ETRIG3 0 input option is available see device specification else ETRISEL is ignored that means external trigger source is still on one of the AD channels selected by ETRIGCH3 0 1 0 0 0 1 ETRIG11 1 0 0 1 0 ETR...

Page 255: ...gger Mode Enable This bit enables the external trigger on one of the AD channels or one of the ETRIG3 0 inputs as described in Table 8 5 If the external trigger source is one of the AD channels the digital input buffer of this channel is enabled The external trigger allows to synchronize the start of conversion with external events 0 Disable external trigger 1 Enable external trigger 1 ASCIE ATD S...

Page 256: ...onversion sequence sequential conversion results are placed in consecutive result registers In a continuously scanning conversion sequence the result register counter will wrap around when it reaches the end of the result register file The conversion counter value CC3 0 in ATDSTAT0 can be used to determine where in the result register file the current conversion result will be placed Aborting a co...

Page 257: ...018 0 016 0 014 0 012 0 010 0 008 0 006 0 004 0 003 0 002 0 000 255 1 1 1 1 1 1 1 0 0 0 0 0 0 1023 4 4 4 3 3 2 2 2 1 1 1 0 0 Table 8 10 Conversion Sequence Length Coding S8C S4C S2C S1C Number of Conversions per Sequence 0 0 0 0 12 0 0 0 1 1 0 0 1 0 2 0 0 1 1 3 0 1 0 0 4 0 1 0 1 5 0 1 1 0 6 0 1 1 1 7 1 0 0 0 8 1 0 0 1 9 1 0 1 0 10 1 0 1 1 11 1 1 0 0 12 1 1 0 1 12 1 1 1 0 12 1 1 1 1 12 Table 8 11 A...

Page 258: ...ple Time Select These three bits select the length of the sample time in units of ATD conversion clock cycles Note that the ATD conversion clock period is itself a function of the prescaler value bits PRS4 0 Table 8 13 lists the available sample time lengths 4 0 PRS 4 0 ATD Clock Prescaler These 5 bits are the binary prescaler value PRS The ATD conversion clock frequency is calculated as follows R...

Page 259: ... 1 Continuous conversion sequences scan mode 4 MULT Multi Channel Sample Mode When MULT is 0 the ATD sequence controller samples only from the specified analog input channel for an entire conversion sequence The analog channel is selected by channel selection code control bits CD CC CB CA located in ATDCTL5 When MULT is 1 the ATD sequence controller samples across channels The number of channels s...

Page 260: ... 1 0 AN2 0 0 1 1 AN3 0 1 0 0 AN4 0 1 0 1 AN5 0 1 1 0 AN6 0 1 1 1 AN7 1 0 0 0 AN8 1 0 0 1 AN9 1 0 1 0 AN10 1 0 1 1 AN11 1 1 0 0 AN11 1 1 0 1 AN11 1 1 1 0 AN11 1 1 1 1 AN11 1 0 0 0 0 Internal_6 Temperature sense of ADC hardmacro 0 0 0 1 Internal_7 0 0 1 0 Internal_0 0 0 1 1 Internal_1 0 1 0 0 VRH 0 1 0 1 VRL 0 1 1 0 VRH VRL 2 0 1 1 1 Reserved 1 0 0 0 Internal_2 1 0 0 1 Internal_3 1 0 1 0 Internal_4 ...

Page 261: ...ensitive mode ETRIGLE 0 if additional active edges are detected while a conversion sequence is in process the overrun flag is set This flag is cleared when one of the following occurs A Write 1 to ETORF B Write to ATDCTL0 1 2 3 4 ATDCMPE or ATDCMPHT a conversion sequence is aborted C Write to ATDCTL5 a new conversion sequence is started 0 No External trigger overrun error has occurred 1 External t...

Page 262: ...nversion or starting a new conversion clears the conversion counter even if FIFO 1 Module Base 0x0008 15 14 13 11 10 9 8 7 6 5 4 3 2 1 0 R 0 0 0 0 CMPE 11 0 W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Unimplemented or Reserved Figure 8 10 ATD Compare Enable Register ATDCMPE Table 8 17 ATDCMPE Field Descriptions Field Description 11 0 CMPE 11 0 Compare Enable for Conversion Number n n 11 10 9 8 7 6 5 4...

Page 263: ...4 CCF 5 is set when the sixth conversion in a sequence is complete and the result is available in ATDDR5 and so forth If automatic compare of conversion results is enabled CMPE n 1 in ATDCMPE the conversion complete flag is only set if comparison with ATDDRn is true If ACMPIE 1 a compare interrupt will be requested In this case as the ATDDRn result register is used to hold the compare value the re...

Page 264: ... is the case W Reset 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 Unimplemented or Reserved Figure 8 12 ATD Input Enable Register ATDDIEN Table 8 19 ATDDIEN Field Descriptions Field Description 11 0 IEN 11 0 ATD Digital Input Enable on channel x x 11 10 9 8 7 6 5 4 3 2 1 0 This bit controls the digital input buffer from the analog input pin ANx to the digital data register 0 Disable digital input buffer to ANx...

Page 265: ...are Operation Higher Than Enable for conversion number n n 11 10 9 8 7 6 5 4 3 2 1 0 of a Sequence n conversion number NOT channel number This bit selects the operator for comparison of conversion results 0 If result of conversion n is lower or same than compare value in ATDDRn this is flagged in ATDSTAT2 1 If result of conversion n is higher than compare value in ATDDRn this is flagged in ATDSTAT...

Page 266: ...are stored in the result registers after each conversion In this case avoid writing to ATDDRn except for initial values because an A D result might be overwritten 8 3 2 12 1 Left Justified Result Data DJM 0 Table 8 21 shows how depending on the A D resolution the conversion result is transferred to the ATD result registers for left justified data Compare is always done using all 12 bits of both th...

Page 267: ... Module Base 0x0010 ATDDR0 0x0012 ATDDR1 0x0014 ATDDR2 0x0016 ATDDR3 0x0018 ATDDR4 0x001A ATDDR5 0x001C ATDDR6 0x001E ATDDR7 0x0020 ATDDR8 0x0022 ATDDR9 0x0024 ATDDR10 0x0026 ATDDR11 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 R 0 0 0 0 Result Bit 11 0 W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Unimplemented or Reserved Figure 8 15 Right justified ATD conversion result register ATDDRn Table 8 22 Conversion...

Page 268: ...t channels to the sample and hold machine 8 4 1 3 Analog to Digital A D Machine The A D Machine performs analog to digital conversions The resolution is program selectable to be either 8 or 10 bits The A D machine uses a successive approximation architecture It functions by comparing the sampled and stored analog voltage with a series of binary coded discrete voltages By following a binary search ...

Page 269: ... to complete another sequence will be triggered immediately 8 4 2 2 General Purpose Digital Port Operation Each ATD input pin can be switched between analog or digital input functionality An analog multiplexer makes each ATD input pin selected as analog input available to the A D converter The pad of the ATD input pin is always connected to the analog input channel of the analog mulitplexer Each p...

Page 270: ...ction see Section 8 3 2 Register Descriptions which details the registers and their bit field 8 6 Interrupts The interrupts requested by the ADC12B12C are listed in Table 8 24 Refer to MCU specification for related vector address and priority See Section 8 3 2 Register Descriptions for further details Table 8 24 ATD Interrupt Vectors Interrupt Source CCR Mask Local Enable Sequence Complete Interru...

Page 271: ...vice specification for exact number Programmable period and duty cycle for each channel Dedicated counter for each PWM channel Programmable PWM enable disable for each channel Software selection of PWM duty pulse polarity for each channel Period and duty cycle are double buffered Change takes effect when the end of the effective period is reached PWM counter reaches zero or when the channel is dis...

Page 272: ... scalable PWM block Figure 9 1 Scalable PWM Block Diagram 9 2 External Signal Description The scalable PWM module has a selected number of external pins Refer to device specification for exact number Period and Duty Counter Channel 6 Clock Select PWM Clock Period and Duty Counter Channel 5 Period and Duty Counter Channel 4 Period and Duty Counter Channel 3 Period and Duty Counter Channel 2 Period ...

Page 273: ... in the register map Reserved bits within a register will always read as 0 and the write will be unimplemented Unimplemented functions are indicated by shading the bit NOTE Register Address Base Address Address Offset where the Base Address is defined at the MCU level and the Address Offset is defined at the module level 9 3 2 Register Descriptions This section describes in detail all the register...

Page 274: ...4 3 2 1 Bit 0 W 0 0 0 0 0 0 0 0 PWMCNT12 R Bit 7 6 5 4 3 2 1 Bit 0 W 0 0 0 0 0 0 0 0 PWMCNT22 R Bit 7 6 5 4 3 2 1 Bit 0 W 0 0 0 0 0 0 0 0 PWMCNT32 R Bit 7 6 5 4 3 2 1 Bit 0 W 0 0 0 0 0 0 0 0 PWMCNT42 R Bit 7 6 5 4 3 2 1 Bit 0 W 0 0 0 0 0 0 0 0 PWMCNT52 R Bit 7 6 5 4 3 2 1 Bit 0 W 0 0 0 0 0 0 0 0 PWMCNT62 R Bit 7 6 5 4 3 2 1 Bit 0 W 0 0 0 0 0 0 0 0 PWMCNT72 R Bit 7 6 5 4 3 2 1 Bit 0 W 0 0 0 0 0 0 0...

Page 275: ...MPER62 R Bit 7 6 5 4 3 2 1 Bit 0 W PWMPER72 R Bit 7 6 5 4 3 2 1 Bit 0 W PWMDTY02 R Bit 7 6 5 4 3 2 1 Bit 0 W PWMDTY12 R Bit 7 6 5 4 3 2 1 Bit 0 W PWMDTY22 R Bit 7 6 5 4 3 2 1 Bit 0 W PWMDTY32 R Bit 7 6 5 4 3 2 1 Bit 0 W PWMDTY42 R Bit 7 6 5 4 3 2 1 Bit 0 W PWMDTY52 R Bit 7 6 5 4 3 2 1 Bit 0 W PWMDTY62 R Bit 7 6 5 4 3 2 1 Bit 0 W PWMDTY72 R Bit 7 6 5 4 3 2 1 Bit 0 W Register Name Bit 7 6 5 4 3 2 1 ...

Page 276: ...gister enabling disabling the corresponding 16 bit PWM channel is controlled by the low order PWMEx bit In this case the high order bytes PWMEx bits have no effect and their corresponding PWM output lines are disabled While in run mode if all existing PWM channels are disabled PWMEx 0 0 the prescaler counter shuts off for power savings Read Anytime Write Anytime RESERVED R 0 0 0 0 0 0 0 0 W RESERV...

Page 277: ...th channel 5 is disabled 1 Pulse width channel 5 is enabled The pulse modulated signal becomes available at PWM output bit 5 when its clock source begins its next cycle 4 PWME4 Pulse Width Channel 4 Enable 0 Pulse width channel 4 is disabled 1 Pulse width channel 4 is enabled The pulse modulated signal becomes available at PWM output bit 4 when its clock source begins its next cycle If CON45 1 the...

Page 278: ... a truncated or stretched pulse can occur during the transition 7 6 5 4 3 2 1 0 R PPOL7 PPOL6 PPOL5 PPOL4 PPOL3 PPOL2 PPOL1 PPOL0 W Reset 0 0 0 0 0 0 0 0 Figure 9 4 PWM Polarity Register PWMPOL Table 9 3 PWMPOL Field Descriptions Note Bits related to available channels have functional significance Writing to unavailable bits has no effect Read from unavailable bits return a zero Field Description ...

Page 279: ...scale is changed while a PWM signal is being generated a truncated or stretched pulse can occur during the transition Table 9 4 PWMCLK Field Descriptions Note Bits related to available channels have functional significance Writing to unavailable bits has no effect Read from unavailable bits return a zero Field Description 7 0 PCLK 7 0 Pulse Width Channel 7 0 Clock Select 0 Clock A or B is the cloc...

Page 280: ...which can be used for all channels These three bits determine the rate of clock B as shown in Table 9 8 2 0 PCKA 2 0 Prescaler Select for Clock A Clock A is one of two clock sources which can be used for all channels These three bits determine the rate of clock A as shown in Table 9 8 Table 9 8 Clock A or Clock B Prescaler Selects PCKA B2 PCKA B1 PCKA B0 Value of Clock A B 0 0 0 bus clock 0 0 1 bu...

Page 281: ...ON23 CON01 PSWAI PFRZ 0 0 W Reset 0 0 0 0 0 0 0 0 Unimplemented or Reserved Figure 9 8 PWM Control Register PWMCTL Table 9 10 PWMCTL Field Descriptions Note Bits related to available channels have functional significance Writing to unavailable bits has no effect Read from unavailable bits return a zero Field Description 7 CON67 Concatenate Channels 6 and 7 0 Channels 6 and 7 are separate 8 bit PWM...

Page 282: ...able bit determines the output mode 3 PSWAI PWM Stops in Wait Mode Enabling this bit allows for lower power consumption in wait mode by disabling the input clock to the prescaler 0 Allow the clock to the prescaler to continue while in wait mode 1 Stop the input clock to the prescaler whenever the MCU is in wait mode 2 PFRZ PWM Counters Stop in Freeze Mode In freeze mode there is an option to disab...

Page 283: ...nnel 6 Clock A B Select 0 Clock B or SB is the clock source for PWM channel 6 as shown in Table 9 6 1 Clock A or SA is the clock source for PWM channel 6 as shown in Table 9 6 5 PCLKAB5 Pulse Width Channel 5 Clock A B Select 0 Clock A or SA is the clock source for PWM channel 5 as shown in Table 9 5 1 Clock B or SB is the clock source for PWM channel 5 as shown in Table 9 5 4 PCLKAB4 Pulse Width C...

Page 284: ... counter to load the new scale value PWMSCLB Read Anytime Write Anytime causes the scale counter to load the PWMSCLB value 9 3 2 10 PWM Channel Counter Registers PWMCNTx Each channel has a dedicated 8 bit up down counter which runs at the rate of the selected clock source The counter can be read at any time without affecting the count or the operation of the PWM channel In left aligned output mode...

Page 285: ...exist Writes to a reserved register have no functional effect Reads from a reserved register return zeroes Read Anytime Write Anytime any value written causes PWM counter to be reset to 00 9 3 2 11 PWM Channel Period Registers PWMPERx There is a dedicated period register for each channel The value in this register determines the period of the associated PWM channel The period registers for each ch...

Page 286: ...e in this register determines the duty of the associated PWM channel The duty value is compared to the counter and if it is equal to the counter value a match occurs and the output changes state The duty registers for each channel are double buffered so that if they change while the channel is enabled the change will NOT take effect until one of the following occurs The effective period ends The c...

Page 287: ... if that channel does not exist Writes to a reserved register have no functional effect Reads from a reserved register return zeroes Read Anytime Write Anytime 9 4 Functional Description 9 4 1 PWM Clock Select There are four available clocks clock A clock B clock SA scaled A and clock SB scaled B These four clocks are based on the bus clock Clock A and B can be software selected to be 1 1 2 1 4 1 ...

Page 288: ... clock B are scaled values of the input clock The value is software selectable for both clock A and clock B and has options of 1 1 2 1 4 1 8 1 16 1 32 1 64 or 1 128 times the bus clock The value selected for clock A is determined by the PCKA2 PCKA1 PCKA0 bits in the PWMPRCLK register The value selected for clock B is determined by the PCKB2 PCKB1 PCKB0 bits also in the PWMPRCLK register 9 4 1 2 Cl...

Page 289: ...WM Ch 0 M U X Clock to PWM Ch 2 M U X Clock to PWM Ch 1 M U X Clock to PWM Ch 4 M U X Clock to PWM Ch 5 M U X Clock to PWM Ch 6 M U X Clock to PWM Ch 7 M U X Clock to PWM Ch 3 Load DIV 2 PWMSCLB Clock SB Clock B 2 B 4 B 6 B 512 M U X PCKA2 PCKA1 PCKA0 PWME7 0 Count 1 Load DIV 2 PWMSCLA Count 1 8 Bit Down Counter 8 Bit Down Counter Prescaler Taps Maximum possible channels scalable in pairs from PWM...

Page 290: ...d by 4 A pulse will occur at a rate of once every 255x4 bus cycles Passing this through the divide by two circuit produces a clock signal at an bus clock divided by 2040 rate Similarly a value of 01 in the PWMSCLA register when clock A is bus clock divided by 4 will produce a clock at an bus clock divided by 8 rate Writing to PWMSCLA or PWMSCLB causes the associated 8 bit down counter to be re loa...

Page 291: ... the block diagram for the PWM timer Figure 9 16 PWM Timer Channel Block Diagram 9 4 2 1 PWM Enable Each PWM channel has an enable bit PWMEx to start its waveform output When any of the PWMEx bits are set PWMEx 1 the associated PWM output signal is enabled immediately However the actual PWM waveform is not available on the associated PWM output until its clock source begins its next cycle due to t...

Page 292: ...be either the old waveform or the new waveform not some variation in between If the channel is not enabled then writes to the period and duty registers will go directly to the latches as well as the buffer A change in duty or period can be forced into effect immediately by writing the new value to the duty and or period registers and then writing to the counter This forces the counter to reset and...

Page 293: ...arted immediately with the output set according to the polarity bit NOTE Writing to the counter while the channel is enabled can cause an irregular PWM cycle to occur The counter is cleared at the end of the effective period see Section 9 4 2 5 Left Aligned Outputs and Section 9 4 2 6 Center Aligned Outputs for more details 9 4 2 5 Left Aligned Outputs The PWM timer provides the choice of two type...

Page 294: ...r channel take the selected clock source frequency for the channel A B SA or SB and divide it by the value in the period register for that channel PWMx Frequency Clock A B SA or SB PWMPERx PWMx Duty Cycle high time as a of period Polarity 0 PPOLx 0 Duty Cycle PWMPERx PWMDTYx PWMPERx 100 Polarity 1 PPOLx 1 Duty Cycle PWMDTYx PWMPERx 100 As an example of a left aligned output consider the following ...

Page 295: ...ection from an up count to a down count When the PWM counter decrements and matches the duty register again the output flip flop changes state causing the PWM output to also change state When the PWM counter decrements and reaches zero the counter direction changes from a down count back to an up count and a load from the double buffer period and duty registers to the associated registers is perfo...

Page 296: ...put waveform generated Figure 9 20 PWM Center Aligned Output Example Waveform 9 4 2 7 PWM 16 Bit Functions The scalable PWM timer also has the option of generating up to 8 channels of 8 bits or 4 channels of 16 bits for greater PWM resolution This 16 bit channel option is achieved through the concatenation of two 8 bit channels The PWMCTL register contains four control bits each of which is used t...

Page 297: ...e channel When using the 16 bit concatenated mode the clock source is determined by the low order 8 bit channel clock select control bits That is channel 7 when channels 6 and 7 are concatenated channel 5 when channels 4 and 5 are concatenated channel 3 when channels 2 and 3 are concatenated and channel 1 when channels 0 and 1 are concatenated The resulting PWM is output to the pins of the corresp...

Page 298: ...hannel is controlled by the low order PWMEx bit In this case the high order bytes PWMEx bits have no effect and their corresponding PWM output is disabled PWMCNT6 PWMCNT7 PWM7 Clock Source 7 High Low Period Duty Compare PWMCNT4 PWMCNT5 PWM5 Clock Source 5 High Low Period Duty Compare PWMCNT2 PWMCNT3 PWM3 Clock Source 3 High Low Period Duty Compare PWMCNT0 PWMCNT1 PWM1 Clock Source 1 High Low Perio...

Page 299: ...d 8 bit normal or 16 bit concatenation 9 5 Resets The reset state of each individual bit is listed within the Section 9 3 2 Register Descriptions which details the registers and their bit fields All special functions or modes which are initialized during or just following reset are described within this section The 8 bit up down counter is configured as an up counter out of reset Table 9 13 16 bit...

Page 300: ...ce Manual Rev 1 3 300 NXP Semiconductors All the channels are disabled and all the counters do not count For channels 0 1 4 and 5 the clock choices are clock A For channels 2 3 6 and 7 the clock choices are clock B 9 6 Interrupts The PWM module has no interrupt ...

Page 301: ...nt Bit NRZ Non Return to Zero RZI Return to Zero Inverted RXD Receive Pin SCI Serial Communication Interface TXD Transmit Pin Table 10 1 Revision History Version Number Revision Date Effective Date Author Description of Changes 06 05 02 22 2013 fix typo Figure 10 1 10 303 Figure 10 4 10 306 update Table 10 2 10 306 10 4 4 10 320 10 4 6 3 10 327 06 06 03 11 2013 fix typo of BDL reset value Figure 1...

Page 302: ...arity for transmitter and receiver Programmable transmitter output parity Two receiver wakeup methods Idle line wakeup Address mark wakeup Interrupt driven operation with eight flags Transmitter empty Transmission complete Receiver full Idle receiver input Receiver overrun Noise error Framing error Parity error Receive wakeup on active edge Transmit collision detect supporting LIN Break Detect sup...

Page 303: ...n blocks Figure 10 1 SCI Block Diagram SCI Data Register RXD Data In Data Out TXD Receive Shift Register Infrared Decoder Receive Wakeup Control Data Format Control Transmit Control Bus Clock 1 16 Transmit Shift Register SCI Data Register Receive Interrupt Generation Transmit Interrupt Generation Infrared Encoder IDLE RDRF OR TC TDRE BRKD BERR RXEDG SCI Interrupt Request Baud Rate Generator Receiv...

Page 304: ...in receives SCI standard or infrared data An idle line is detected as a line high This input is ignored when the receiver is disabled and should be terminated to a known voltage 10 3 Memory Map and Register Definition This section provides a detailed description of all the SCI registers 10 3 1 Module Memory Map and Register Definition The memory map for the SCI module is given below in Figure 10 2...

Page 305: ...BR12 SBR11 SBR10 SBR9 SBR8 W SCIBDL1 R SBR7 SBR6 SBR5 SBR4 SBR3 SBR2 SBR1 SBR0 W SCICR11 R LOOPS SCISWAI RSRC M WAKE ILT PE PT W SCIASR12 R RXEDGIF 0 0 0 0 BERRV BERRIF BKDIF W SCIACR12 R RXEDGIE 0 0 0 0 0 BERRIE BKDIE W SCIACR22 R IREN TNP1 TNP0 0 0 BERRM1 BERRM0 BKDFE W SCICR2 R TIE TCIE RIE ILIE TE RE RWU SBK W SCISR1 R TDRE TC RDRF IDLE OR NF FE PF W SCISR2 R AMAP 0 0 TXPOL RXPOL BRK13 TXDIR R...

Page 306: ...egister SCIBDL Table 10 2 SCIBDH and SCIBDL Field Descriptions Field Description SBR 15 0 SCI Baud Rate Bits The baud rate for the SCI is determined by the bits in this register The baud rate is calculated two different ways depending on the state of the IREN bit The formulas for calculating the baud rate are When IREN 0 then SCI baud rate SCI bus clock SBR 15 0 When IREN 1 then SCI baud rate SCI ...

Page 307: ...LOOPS 1 the RSRC bit determines the source for the receiver shift register input See Table 10 4 0 Receiver input internally connected to transmitter output 1 Receiver input connected externally to transmitter 4 M Data Format Mode Bit MODE determines whether data characters are eight or nine bits long 0 One start bit eight data bits one stop bit 1 One start bit nine data bits one stop bit 3 WAKE Wa...

Page 308: ...generates and checks for even parity or odd parity With even parity an even number of 1s clears the parity bit and an odd number of 1s sets the parity bit With odd parity an odd number of 1s clears the parity bit and an even number of 1s sets the parity bit 0 Even parity 1 Odd parity Table 10 4 Loop Functions LOOPS RSRC Function 0 x Normal operation 1 0 Loop mode with transmitter output internally...

Page 309: ...alue BERRV reflects the state of the RXD input when the bit error detect circuitry is enabled and a mismatch to the expected value happened The value is only meaningful if BERRIF 1 0 A low input was sampled when a high was expected 1 A high input reassembled when a low was expected 1 BERRIF Bit Error Interrupt Flag BERRIF is asserted when the bit error detect circuitry is enabled and if the value ...

Page 310: ...on 7 RXEDGIE Receive Input Active Edge Interrupt Enable RXEDGIE enables the receive input active edge interrupt flag RXEDGIF to generate interrupt requests 0 RXEDGIF interrupt requests disabled 1 RXEDGIF interrupt requests enabled 1 BERRIE Bit Error Interrupt Enable BERRIE enables the bit error interrupt flag BERRIF to generate interrupt requests 0 BERRIF interrupt requests disabled 1 BERRIF inter...

Page 311: ...w Pulse Bits These bits enable whether the SCI transmits a 1 16 3 16 1 32 or 1 4 narrow pulse See Table 10 8 2 1 BERRM 1 0 Bit Error Mode Those two bits determines the functionality of the bit error detect feature See Table 10 9 0 BKDFE Break Detect Feature Enable BKDFE enables the break detect circuitry 0 Break detect circuit disabled 1 Break detect circuit enabled Table 10 8 IRSCI Transmit Pulse...

Page 312: ...d 1 RDRF and OR interrupt requests enabled 4 ILIE Idle Line Interrupt Enable Bit ILIE enables the idle line flag IDLE to generate interrupt requests 0 IDLE interrupt requests disabled 1 IDLE interrupt requests enabled 3 TE Transmitter Enable Bit TE enables the SCI transmitter and configures the TXD pin as being controlled by the SCI The TE bit can be used to queue an idle preamble 0 Transmitter di...

Page 313: ...Complete Flag TC is set low when there is a transmission in progress or when a preamble or break character is loaded TC is set high when the TDRE flag is set and no data preamble or break character is being transmitted When TC is set the TXD pin becomes idle logic 1 Clear TC by reading SCI status register 1 SCISR1 with TC set and then writing to SCI data register low SCIDRL TC is cleared automatic...

Page 314: ... exactly the same time as event 2 or any time after When this happens a dummy SCIDRL read following event 4 will be required to clear the OR flag if further frames are to be received 2 NF Noise Flag NF is set when the SCI detects noise on the receiver input NF bit is set during the same cycle as the RDRF flag but does not get set in the case of an overrun Clear NF by reading SCI status register 1 ...

Page 315: ...aining idle high for a one for inverted polarity 0 Normal polarity 1 Inverted polarity 3 RXPOL Receive Polarity This bit control the polarity of the received data In NRZ format a one is represented by a mark and a zero is represented by a space for normal polarity and the opposite for inverted polarity In IrDA format a zero is represented by short high pulse in the middle of a bit time remaining i...

Page 316: ...s write first to SCI data register high SCIDRH then SCIDRL 7 6 5 4 3 2 1 0 R R8 T8 0 0 0 Reserved Reserved Reserved W Reset 0 0 0 0 0 0 0 0 Unimplemented or Reserved Figure 10 12 SCI Data Registers SCIDRH 7 6 5 4 3 2 1 0 R R7 R6 R5 R4 R3 R2 R1 R0 W T7 T6 T5 T4 T3 T2 T1 T0 Reset 0 0 0 0 0 0 0 0 Figure 10 13 SCI Data Registers SCIDRL Table 10 13 SCIDRH and SCIDRL Field Descriptions Field Description...

Page 317: ...The CPU monitors the status of the SCI writes the data to be transmitted and processes received data Figure 10 14 Detailed SCI Block Diagram SCI Data Receive Shift Register SCI Data Register Transmit Shift Register Register Receive Generator SBR15 SBR0 Bus Transmit Control 16 Receive and Wakeup Data Format Control Control T8 PF FE NF RDRF IDLE TIE OR TCIE TDRE TC R8 RAF LOOPS RWU RE PE ILT PT WAKE...

Page 318: ...uring transmission The infrared block receives two clock sources from the SCI R16XCLK and R32XCLK which are configured to generate the narrow pulse width during transmission The R16XCLK and R32XCLK are internal clocks with frequencies 16 and 32 times the baud rate respectively Both R16XCLK and R32XCLK clocks are used for transmitting data The receive decoder uses only the R16XCLK clock 10 4 1 1 In...

Page 319: ... for 9 bit data characters the ninth data bit is the T8 bit in SCI data register high SCIDRH It remains unchanged after transmission and can be used repeatedly without rewriting it A frame with nine data bits has a total of 11 bits Table 10 14 Example of 8 Bit Data Formats Start Bit Data Bits Address Bits Parity Bits Stop Bit 1 8 0 0 1 1 7 0 1 1 1 7 11 1 The address bit identifies the frame as an ...

Page 320: ...tion rate of 16 samples per bit time Baud rate generation is subject to one source of error Integer division of the bus clock may not give the exact target frequency Table 10 16 lists some examples of achieving target baud rates with a bus clock frequency of 25 MHz When IREN 0 then SCI baud rate SCI bus clock SCIBR 15 0 1 The address bit identifies the frame as an address character See Section 10 ...

Page 321: ...CIDRL which in turn are transferred to the transmitter shift register The transmit shift register then shifts a frame out through the TXD pin after it has prefaced them with a start bit and appended them with a stop bit The SCI data registers SCIDRH and SCIDRL are the write only buffers between the internal data bus and the transmit shift register PE PT H 8 7 6 5 4 3 2 1 0 L 11 Bit Transmit Regist...

Page 322: ...H L where the ninth bit is written to the T8 bit in SCIDRH if the SCI is in 9 bit data format A new transmission will not result until the TDRE flag has been cleared 3 Repeat step 2 for each subsequent transmission NOTE The TDRE flag is set when the shift register is loaded with the next data to be transmitted from SCIDRH L which happens generally speaking a little over half way through the stop b...

Page 323: ... Break character length depends on the M bit in SCI control register 1 SCICR1 As long as SBK is at logic 1 transmitter logic continuously loads break characters into the transmit shift register After software clears the SBK bit the shift register finishes transmitting the last break character and then transmits at least one logic 1 The automatic logic 1 at the end of a break character guarantees t...

Page 324: ...amble contains all logic 1s and has no start stop or parity bit Idle character length depends on the M bit in SCI control register 1 SCICR1 The preamble is a synchronizing idle character that begins the first transmission initiated after writing the TE bit from 0 to 1 If the TE bit is cleared during a transmission the TXD pin becomes idle after completion of the transmission in progress Clearing a...

Page 325: ...d the byte in transmit buffer is discarded the transmit data register empty and the transmission complete flag will be set The bit error interrupt flag BERRIF will be set No further transmissions will take place until the BERRIF is cleared Figure 10 19 Timing Diagram Bit Error Detection If the bit error detect feature is disabled the bit error interrupt flag is cleared NOTE The RXPOL and TXPOL bit...

Page 326: ...SCI data register is the read only buffer between the internal data bus and the receive shift register After a complete frame shifts into the receive shift register the data portion of the frame transfers to the SCI data register The receive data register full flag RDRF in SCI status register 1 SCISR1 becomes set All 1s M WAKE ILT PE PT RE H 8 7 6 5 4 3 2 1 0 L 11 Bit Receive Shift Register Stop S...

Page 327: ...gic 0 To locate the start bit data recovery logic does an asynchronous search for a logic 0 preceded by three logic 1s When the falling edge of a possible start bit occurs the RT clock begins to count to 16 Figure 10 21 Receiver Data Sampling To verify the start bit and to detect noise data recovery logic takes samples at RT3 RT5 and RT7 Figure 10 17 summarizes the results of the start bit verific...

Page 328: ...s are logic 1s following a successful start bit verification the noise flag NF is set and the receiver assumes that the bit is a start bit logic 0 To verify a stop bit and to detect noise recovery logic takes samples at RT8 RT9 and RT10 Table 10 19 summarizes the results of the stop bit samples Table 10 18 Data Bit Recovery RT8 RT9 and RT10 Samples Data Bit Determination Noise Flag 000 0 0 001 0 1...

Page 329: ...T3 is high The RT3 sample sets the noise flag Although the perceived bit time is misaligned the data samples RT8 RT9 and RT10 are within the bit time and data recovery is successful Figure 10 23 Start Bit Search Example 2 Reset RT Clock RT1 RT1 RT1 RT1 RT2 RT3 RT4 RT5 RT1 RT1 RT2 RT3 RT4 RT7 RT6 RT5 RT10 RT9 RT8 RT14 RT13 RT12 RT11 RT15 RT16 RT1 RT2 RT3 Samples RT Clock RT Clock Count Start Bit RX...

Page 330: ...0 25 shows the effect of noise early in the start bit time Although this noise does not affect proper synchronization with the start bit time it does set the noise flag Figure 10 25 Start Bit Search Example 4 Reset RT Clock RT1 RT1 RT1 RT1 RT2 RT3 RT4 RT5 RT6 RT7 RT8 RT9 RT10 RT13 RT12 RT11 RT16 RT15 RT14 RT4 RT3 RT2 RT1 RT5 RT6 RT7 RT8 RT9 Samples RT Clock RT Clock Count Actual Start Bit RXD 1 0 ...

Page 331: ... and RT10 data samples are ignored Figure 10 27 Start Bit Search Example 6 10 4 6 4 Framing Errors If the data recovery logic does not detect a logic 1 where the stop bit should be in an incoming frame it sets the framing error flag FE in SCI status register 1 SCISR1 A break character also sets the FE flag because a break character has no stop bit The FE flag is set at the same time that the RDRF ...

Page 332: ...rrives in time for the stop bit data samples at RT8 RT9 and RT10 Figure 10 28 Slow Data Let s take RTr as receiver RT clock and RTt as transmitter RT clock For an 8 bit data character it takes the receiver 9 bit times x 16 RTr cycles 7 RTr cycles 151 RTr cycles to start data sampling of the stop bit With the misaligned character shown in Figure 10 28 the receiver counts 151 RTr cycles at the point...

Page 333: ...ver counts 169 RTr cycles at the point when the count of the transmitting device is 11 bit times x 16 RTt cycles 176 RTt cycles The maximum percent difference between the receiver count and the transmitter count of a fast 9 bit character with no errors is 176 169 176 x 100 3 98 NOTE Due to asynchronous sample and internal logic there is maximal 2 bus cycles between startbit edge and 1st RT clock a...

Page 334: ...e receive data register full flag RDRF The idle line type bit ILT determines whether the receiver begins counting logic 1s as idle character bits after the start bit or after the stop bit ILT is in SCI control register 1 SCICR1 10 4 6 6 2 Address Mark Wakeup WAKE 1 In this wakeup method a logic 1 in the most significant bit MSB position of a frame clears the RWU bit and wakes up the SCI The logic ...

Page 335: ...tion data from the TXD pin is inverted if RXPOL is set 10 4 8 Loop Operation In loop operation the transmitter output goes to the receiver input The RXD pin is disconnected from the SCI Figure 10 31 Loop Operation LOOPS 1 RSRC 0 Enable loop operation by setting the LOOPS bit and clearing the RSRC bit in SCI control register 1 SCICR1 Setting the LOOPS bit disables the path from the RXD pin to the r...

Page 336: ...uced power consumption The STOP instruction does not affect the SCI register states but the SCI bus clock will be disabled The SCI operation resumes from where it left off after an external interrupt brings the CPU out of stop mode Exiting stop mode by reset aborts any transmission or reception in progress and resets the SCI The receive input active edge detect circuit is still active in stop mode...

Page 337: ...dicates that an active edge falling for RXPOL 0 rising for RXPOL 1 was detected BERRIF SCIASR1 1 BERRIE Active high level Indicates that a mismatch between transmitted and received data in a single wire application has happened BKDIF SCIASR1 0 BRKDIE Active high level Indicates that a break character has been received Table 10 20 SCI Interrupt Sources ...

Page 338: ...indicates that there is no transmission in progress TC is set high when the TDRE flag is set and no data preamble or break character is being transmitted When TC is set the TXD pin becomes idle logic 1 Clear TC by reading SCI status register 1 SCISR1 with TC set and then writing to SCI data register low SCIDRL TC is cleared automatically when data preamble or break is queued and ready to be sent 1...

Page 339: ...ata in a single wire application like LIN was detected Clear BERRIF by writing a 1 to the SCIASR1 SCI alternative status register 1 This flag is also cleared if the bit error detect feature is disabled 10 5 3 1 8 BKDIF Description The BKDIF interrupt is set when a break signal was received Clear BKDIF by writing a 1 to the SCIASR1 SCI alternative status register 1 This flag is also cleared if brea...

Page 340: ...Serial Communication Interface S12SCIV6 MC9S12VRP Family Reference Manual Rev 1 3 340 NXP Semiconductors ...

Page 341: ...ss for the counter registers or the input capture output compare registers should take place in one clock cycle Accessing high byte and low byte separately for all of these registers may not yield the same result as accessing them in one word 11 1 1 Features The TIM16B2CV3 includes these distinctive features Up to 2 channels available refer to device specification for exact number All channels hav...

Page 342: ... for exact number 11 2 1 IOC1 IOC0 Input Capture and Output Compare Channel 1 0 Those pins serve as input capture or output compare for TIM16B2CV3 channel NOTE For the description of interrupts see Section 11 6 Interrupts Prescaler 16 bit Counter Input capture Output compare IOC0 IOC1 Timer overflow interrupt Timer channel 0 interrupt Timer channel 1 interrupt Registers Bus clock Input capture Out...

Page 343: ...ESERV ED RESERV ED RESERV ED RESERV ED RESERV ED RESERV ED IOS1 IOS0 W 0x0001 CFORC R 0 0 0 0 0 0 0 0 W RESERV ED RESERV ED RESERV ED RESERV ED RESERV ED RESERV ED FOC1 FOC0 0x0004 TCNTH R TCNT15 TCNT14 TCNT13 TCNT12 TCNT11 TCNT10 TCNT9 TCNT8 W 0x0005 TCNTL R TCNT7 TCNT6 TCNT5 TCNT4 TCNT3 TCNT2 TCNT1 TCNT0 W 0x0006 TSCR1 R TEN TSWAI TSFRZ TFFCA PRNT 0 0 0 W 0x0007 TTOV R RESERV ED RESERV ED RESERV...

Page 344: ...PS4 PTPS3 PTPS2 PTPS1 PTPS0 W 0x002F Reserved R W 1 The register is available only if corresponding channel exists 7 6 5 4 3 2 1 0 R RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED IOS1 IOS0 W Reset 0 0 0 0 0 0 0 0 Figure 11 4 Timer Input Capture Output Compare Select TIOS Table 11 2 TIOS Field Descriptions Note Writing to unavailable bits has no effect Reading from unavailable bits return a...

Page 345: ...FORC Field Descriptions Note Writing to unavailable bits has no effect Reading from unavailable bits return a zero Field Description 1 0 FOC 1 0 Note Force Output Compare Action for Channel 1 0 A write to this register with the corresponding data bit s set causes the action which is programmed for output compare x to occur immediately The action taken is the same as if a successful comparison had ...

Page 346: ... in the wait mode Timer interrupts cannot be used to get the MCU out of wait TSWAI also affects pulse accumulator 5 TSFRZ Timer Stops While in Freeze Mode 0 Allows the timer counter to continue running while in freeze mode 1 Disables the timer counter whenever the MCU is in freeze mode This is useful for emulation TSFRZ does not stop the pulse accumulator 4 TFFCA Timer Fast Flag Clear All 0 Allows...

Page 347: ...e bits has no effect Reading from unavailable bits return a zero Field Description 1 0 TOV 1 0 Toggle On Overflow Bits TOVx toggles output compare pin on overflow This feature only takes effect when in output compare mode When set it takes precedence over forced output compare 0 Toggle output compare pin on overflow feature disabled 1 Toggle output compare pin on overflow feature enabled 7 6 5 4 3...

Page 348: ...x must be cleared 1 0 OLx Output Level These two pairs of control bits are encoded to specify the output action to be taken as a result of a successful OCx compare When either OMx or OLx is 1 the pin associated with OCx becomes an output tied to OCx Note For an output line to be driven by an OCx the OCPDx must be cleared Table 11 7 Compare Result Output Action OMx OLx Action 0 0 No output compare ...

Page 349: ...nly 1 0 Capture on falling edges only 1 1 Capture on any edge rising or falling 7 6 5 4 3 2 1 0 R RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED C1I C0I W Reset 0 0 0 0 0 0 0 0 Figure 11 14 Timer Interrupt Enable Register TIE Table 11 10 TIE Field Descriptions Note Writing to unavailable bits has no effect Reading from unavailable bits return a zero Field Description 1 0 C1I C0I Input Captu...

Page 350: ...11 TSCR2 Field Descriptions Field Description 7 TOI Timer Overflow Interrupt Enable 0 Interrupt inhibited 1 Hardware interrupt requested when TOF flag set 2 0 PR 2 0 Timer Prescaler Select These three bits select the frequency of the timer prescaler clock derived from the Bus Clock as shown in Table 11 12 Table 11 12 Timer Clock Selection PR2 PR1 PR0 Timer Clock 0 0 0 Bus Clock 1 0 0 1 Bus Clock 2...

Page 351: ...n 1 0 C 1 0 F Input Capture Output Compare Channel x Flag These flags are set when an input capture or output compare event occurs Clearing requires writing a one to the corresponding flag bit while TEN is set to one Note When TFFCA bit in TSCR register is set a read from an input capture or a write into an output compare channel 0x0010 0x001F will cause the corresponding channel flag CxF to be cl...

Page 352: ...Anytime Write Anytime for output compare function Writes to these registers have no meaning or effect during input capture All timer input capture output compare registers are reset to 0x0000 NOTE Read Write access in byte mode for high byte should take place before low byte otherwise it will give a different result 11 3 2 13 Output Compare Pin Disconnect Register OCPD 15 14 13 12 11 10 9 0 R Bit ...

Page 353: ...are action will occur on the channel pin These bits do not affect the input capture 1 Disables the timer channel port Output Compare action will not occur on the channel pin but the output compare flag still become set 7 6 5 4 3 2 1 0 R PTPS7 PTPS6 PTPS5 PTPS4 PTPS3 PTPS2 PTPS1 PTPS0 W Reset 0 0 0 0 0 0 0 0 Figure 11 21 Precision Timer Prescaler Select Register PTPSR Table 11 16 PTPSR Field Descri...

Page 354: ...ption of the timer TIM16B2CV3 block Please refer to the detailed timer block diagram in Figure 11 22 as necessary 0 0 0 0 0 0 0 1 2 0 0 0 0 0 0 1 0 3 0 0 0 0 0 0 1 1 4 0 0 0 1 0 0 1 1 20 0 0 0 1 0 1 0 0 21 0 0 0 1 0 1 0 1 22 1 1 1 1 1 1 0 0 253 1 1 1 1 1 1 0 1 254 1 1 1 1 1 1 1 0 255 1 1 1 1 1 1 1 1 256 PTPS7 PTPS6 PTPS5 PTPS4 PTPS3 PTPS2 PTPS1 PTPS0 Prescale Factor ...

Page 355: ...alue that generates a divide by 1 2 4 8 16 32 64 and 128 when the PRNT bit in TSCR1 is disabled PRESCALER CHANNEL 0 IOC0 PIN 16 BIT COUNTER LOGIC PR 2 1 0 TC0 16 BIT COMPARATOR TCNT hi TCNT lo CHANNEL 1 TC1 16 BIT COMPARATOR INTERRUPT LOGIC TOF TOI C0F C1F EDGE DETECT IOC1 PIN LOGIC EDGE DETECT CxF CHANNELn 1 TCn 1 16 BIT COMPARATOR Cn 1F IOCn 1 PIN LOGIC EDGE DETECT OM OL0 TOV0 OM OL1 TOV1 OM OLn...

Page 356: ...th a programmable polarity duration and frequency When the timer counter reaches the value in the channel registers of an output compare channel the timer can set clear or toggle the channel pin if the corresponding OCPDx bit is set to zero An output compare on channel x sets the CxF flag The CxI bit enables the CxF flag to generate interrupt requests Timer module must stay enabled TEN bit of TSCR...

Page 357: ...16B2CV3 to communicate with the MCU The TIM16B2CV3 could use up to 3 interrupt vectors The interrupt vector offsets and interrupt numbers are chip dependent 11 6 1 Channel 1 0 Interrupt C 1 0 F This active high outputs will be asserted by the module to request a timer channel 7 0 interrupt The TIM block only generates the interrupt and does not service it Only bits related to implemented channels ...

Page 358: ...Timer Module TIM16B2CV3 MC9S12VRP Family Reference Manual Rev 1 3 358 NXP Semiconductors ...

Page 359: ...x register bits or PWM or timer channels Open load detection Slew rate control Over current shutdown comprising of Interrupt flag generation Driver shutdown Rev No Item No Date Submitted By Sections Affected Substantial Change s V1 00 10 December 2010 All Initial V2 00 07 Sep 2012 All Added description and register bits for over current masking feature V2 02 05 August 2013 All Removed open load de...

Page 360: ...p mode the drivers are re enabled and the state of the HSCR HSEx bits is restored automatically If the data register bits HSDR HSDRx are chosen as source in the PIM module then the respective high side driver stays turned off until the software sets the associated bit in the data register HSDR HSDRx When the timer or PWM are chosen as source the respective high side driver is controlled by the tim...

Page 361: ...ers intended to drive LEDs or resistive loads 12 2 2 VSUPHS High Side Driver Power Pin Power supply for the high side driver This pin must be connected to the main power supply with the appropriate reverse battery protection network Table 12 2 HSDRV2C Signal Properties Name Function Reset State HS 1 0 High side driver outputs 0 1 disabled off VSUPHS High Voltage Power Supply for both high side dri...

Page 362: ...er Address Module Base Address Address Offset where the Module Base Address is defined at the MCU level and the Address Offset is defined at the module level Table 12 3 Register Summary Address Offset Register Name Bit 7 6 5 4 3 2 1 Bit 0 0x0000 HSDR R 0 0 0 0 0 0 HSDR1 HSDR0 W 0x0001 HSCR R 0 0 HSOCME1 HSOCME0 HSOLE1 HSOLE0 HSE1 HSE0 W 0x0002 HSSLR R 0 0 0 0 HSSLCU1 HSSLCU0 HSSLEN1 HSSLEN0 W 0x00...

Page 363: ... output or routed timer output or routed PWM output This register can be used to control the high side drivers if selected as control source See PIM section for routing details If the associated HSCR HSEx bit is set to 0 a read returns the value of the Port HS Data Register HSDR HSDRx If the associated HSCR HSEx bit is set to 1 a read returns the value of the selected control source for the driver...

Page 364: ...V2C High Load Resistance Open Load Detection Enable These bits enable the measurement function to detect an open load condition on the related high side driver operating on high load resistance loads If the high side driver is enabled and is not being driven by the selected source then the high load resistance detection circuit is activated when this bit is set to 1 0 high load resistance open loa...

Page 365: ... 2 HSSLCUx Slew Current Reduction Enable The maximum output current is reduced for 4 us when the associated driver is switched on to reduce the emission if the high side driver is used as an off board driver These bits are only writable if the associated high side driver is disabled HSCR HSEx 0 0 Slew current reduction disabled 1 Slew current reduction enabled 1 0 HSSLENx Slew Rate Control Enable ...

Page 366: ...in special mode can alter the module s functionality Module Base 0x0003 Access User read write1 1 Read Anytime Write Only in special mode 7 6 5 4 3 2 1 0 R Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved W Reset x x x x x x x x Unimplemented Figure 12 5 Reserved Register Table 12 7 Reserved Register Field Descriptions Field Description 7 0 Reserved These reserved bits are u...

Page 367: ... 0 0 0 0 0 0 Unimplemented Figure 12 6 HSDRV2C Status Register HSSR Table 12 8 HSDRV Status Register HSSR Field Descriptions Field Description 1 0 HSOLx HSDRV2C Open Load Status Bits These bits reflect the open load condition of the associated the driver pin A delay of tHLROLDT must be granted after enabling the high load resistance open load detection function in order to read valid data 0 No ope...

Page 368: ...d write1 1 Read Anytime Write Anytime 7 6 5 4 3 2 1 0 R HSOCIE 0 0 0 0 0 0 0 W Reset 0 0 0 0 0 0 0 0 Unimplemented Figure 12 7 HSDRV2C Interrupt Enable Register HSIE Table 12 9 HSDRV Interrupt Enable Register HSIE Field Descriptions Field Description 7 HSOCIE HSDRV2C Over Current Interrupt Enable 0 Interrupt request is disabled 1Interrupt is requested whenever a HSIF HSOCIFx flag is set ...

Page 369: ...detect an open load condition a small current IHVOLDC will flow through the load If the driving pin HS x stays at a voltage above an internal threshold then an open load will be detected for the associated high side driver The open load condition is flagged in the HSDRV Status Register HSSR Module Base 0x0007 Access User read write1 1 Read Anytime Write Write 1 to clear writing 0 has no effect 7 6...

Page 370: ...driver shutdown can be masked for an initial THSOCM after switching the driver on This can be achieved by setting the associated HSCR HSOCMEx register bit HSCR HSOCMEx is only writable while the associated driver is disabled HSCR HSEx 0 12 4 4 Interrupts This section describes the interrupt generated by HSDRV2C module The interrupt is only available in MCU run mode Entering and exiting MCU stop mo...

Page 371: ... shutdown and interrupt while enabled Active clamp to protect the device against over voltage when the power transistor that is driving an inductive load relay is turned off Rev No Item No Date Submitted By Sections Affected Substantial Change s V01 00 10 December 2010 All Initial Version V1 01 22 February 2011 All Added clarification to open load mechanism in over current conditions V1 02 12 Apri...

Page 372: ...are re enabled If the data register bits LSDR LSDRn were chosen as source in PIM module then the respective low side driver stays turned off until the software sets the associated bit in the data register LSDR LSDRn If the timer or PWM is chosen as source the respective low side driver is controlled by the timer or PWM without further handling If it is required that the driver stays turned off aft...

Page 373: ...s associated with the LSDRV module is shown in Table 13 3 Detailed descriptions of the registers and bits are given in the following sections NOTE Register Address Module Base Address Address Offset where the Module Base Address is defined at the MCU level and the Address Offset is defined at the module level Table 13 2 LSDRV Signal Properties Name Function Reset State LS0 Low side driver output 0...

Page 374: ...Rev 1 3 374 NXP Semiconductors 0x0004 Reserved R 0 0 0 0 0 0 0 0 W 0x0005 LSSR R 0 0 0 0 0 0 LSOL1 LSOL0 W 0x0006 LSIE R LSOCIE 0 0 0 0 0 0 0 W 0x0007 LSIF R 0 0 0 0 0 0 LSOCIF1 LSOCIF0 W Table 13 3 Register Summary Address Offset Register Name Bit 7 6 5 4 3 2 1 Bit 0 ...

Page 375: ...tputs or routed PWM outputs These register bits can be used to control the low side drivers if selected as control source See PIM section for routing details If the associated LSCR LSEn bit is set to 0 a read returns the value of the Port LS Data Register LSDR LSDRn If the associated LSCR LSEn bit is set to 1 a read returns the value of the selected control source for the driver When entering in S...

Page 376: ... to detect an open load condition on the related low side driver operating on high load resistance loads If the low side driver is enabled and is not being driven by the selected source then the high load resistance detection circuit is activated when this bit is set to 1 0 high load resistance open load detection is disabled 1 high load resistance open load detection is enabled 1 0 LSEx LSDRV Ena...

Page 377: ...lity Module Base 0x0002 Access User read write1 1 Read Anytime Write Only in special mode 7 6 5 4 3 2 1 0 R Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved W Reset x x x x x x x x After de assert of System Reset a value is automatically loaded from the Flash Memory Unimplemented Figure 13 4 Reserved Register Table 13 6 Reserved Register Field Description 7 0 Reserved These ...

Page 378: ...set 0 0 0 0 0 0 0 0 Unimplemented Figure 13 6 LSDRV Status Register LSSR Table 13 8 LSSR Register Field Descriptions Field Description 1 0 LSOLx LSDRV Open Load Status Bits These bits reflect the open load condition status on each driver related pin This open load monitoring will only be active if the detection function is enabled bits LSOLEx and the corresponding low side driver is enabled and tu...

Page 379: ...ss User read write1 1 Read Anytime Write Anytime 7 6 5 4 3 2 1 0 R LSOCIE 0 0 0 0 0 0 0 W Reset 0 0 0 0 0 0 0 0 Unimplemented Figure 13 7 LSDRV Interrupt Enable Register LSIE Table 13 9 LSIE Register Field Descriptions Field Description 7 LSOCIE LSDRV Error Interrupt Enable 0 Interrupt request is disabled 1 Interrupt will be requested whenever a LSOCIFx flag is set ...

Page 380: ...V Interrupt Flag Register LSIF Table 13 10 LSIF Register Field Descriptions Field Description 1 0 LSOCIFx LSDRV Over Current Interrupt Flag These flags are set to 1 when an over current event occurs on the related low side driver ILS ILIMLSX A set interrupt flag causes the related low side driver to be turned off Once the interrupt flag is cleared again the associated driver is driven by the sourc...

Page 381: ...ver To detect an open load condition the voltage is observed at the output of the driver If the driving pin LSn with driver turned off stays at low voltage approximately LSGND then there is no load for the corresponding low side driver An open load condition is flagged with LSDRV Status Register bits LSSR LSOL0 and LSSR LSOL1 NOTE The open load detection is only active if the selected source e g P...

Page 382: ...ver over current event is detected the related interrupt flag LSIF LSOCIFn asserts Depending on the setting of the LSDRV Error Interrupt Enable LSIE LSOCIE bit an interrupt is requested Table 13 11 LSDRV Interrupt Sources Module Interrupt Source Module Internal Interrupt Source Local Enable LSDRV Interrupt LSI LSDRV Over Current Interrupt LSOCI LSIE LSOCIE 1 ...

Page 383: ...1 MCU run mode The activation of the LSE bit enables the low side driver The driver is controlled by the selected source in the Port Integration Module see PIM chapter 2 MCU stop mode During stop mode operation the low side drivers are shut down i e the low side drivers are disabled and their drivers are turned off The data register which controls the driver LS2DR iscleared automatically After ret...

Page 384: ...off after the stop mode for this case PWM or timer the software must take the appropriate action to turn off the driver before entering stop mode 14 1 3 Block Diagram Figure 14 1 shows a block diagram of the LS2DRV module The module consists of a control and an output stage Internal functions can be routed to control the low side drivers See PIM chapter for routing options Figure 14 1 LS2DRV Block...

Page 385: ...n in Table 14 3 Detailed descriptions of the registers and bits are given in the following sections NOTE Register Address Module Base Address Address Offset where the Module Base Address is defined at the MCU level and the Address Offset is defined at the module level Table 14 2 LS2DRV Signal Properties Name Function Reset State LS2 Low side driver output disabled off Table 14 3 Register Summary A...

Page 386: ...DRV_V1 MC9S12VRP Family Reference Manual Rev 1 3 386 NXP Semiconductors 0x0006 LS2IE R LS2OCIE 0 0 0 0 0 0 0 W 0x0007 LS2IF R 0 0 0 0 0 0 0 LS2OCIF W Table 14 3 Register Summary Address Offset Register Name Bit 7 6 5 4 3 2 1 Bit 0 ...

Page 387: ...ription 0 LS2DR Port LS Data Bits Data registers or routed timer outputs or routed PWM outputs This register bit can be used to control the low side driver if selected as control source See PIM section for routing details If the associated LS2E bit is set to 0 a read returns the value of the Port LS Data Register LS2DR If the associated LS2E bit is set to 1 a read returns the value of the selected...

Page 388: ...0 LS2E W Reset 0 0 0 0 0 0 0 0 Unimplemented Figure 14 3 LS2DRV Configuration Register LS2CR Table 14 5 LS2CR Register Field Descriptions Field Description 0 LS2E LS2DRV Enable These bits control the bias of the related low side driver circuit 0 Low side driver is disabled 1 Low side driver is enabled NOTE After enabling the low side driver write 1 to LS2E a settling time tLS_settling is required ...

Page 389: ...r when in special mode can alter the module s functionality Module Base 0x0003 Access User read write1 1 Read Anytime Write Only in special mode 7 6 5 4 3 2 1 0 R Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved W Reset x x x x x x x x Unimplemented Figure 14 4 Reserved Register Table 14 6 Reserved Register Field Description 7 0 Reserved These reserved bits are used for test...

Page 390: ...s User read write1 1 Read Anytime Write Anytime 7 6 5 4 3 2 1 0 R LS2OCIE 0 0 0 0 0 0 0 W Reset 0 0 0 0 0 0 0 0 Unimplemented Figure 14 5 LS2DRV Interrupt Enable Register LS2IE Table 14 7 LS2IE Register Field Descriptions Field Description 7 LS2OCIE LS2DRV Error Interrupt Enable 0 Interrupt request is disabled 1 Interrupt will be requested whenever a LS2OCIFx flag is set ...

Page 391: ...gure 14 6 LS2DRV Interrupt Flag Register LS2IF Table 14 8 LS2IF Register Field Descriptions Field Description 0 LS2OCIF LS2DRV Over Current Interrupt Flag These flags are set to 1 when an over current event occurs on the related low side driver ILS ILIMLSX While set the related low side driver is turned off Once these flags are cleared the related driver is again driven by the source selected in P...

Page 392: ...g remains set the related low side driver is turned off to protect the circuit Clearing the related over current interrupt flag returns back the control of the driver to the selected source in the PIM module 14 4 3 Interrupts This section describes the interrupt generated by LS2DRV module The interrupt is only available in MCU run mode Entering and exiting MCU stop mode has no effect on the interr...

Page 393: ...follows in the system power modes In run mode all features are available In wait mode all features are available In stop mode the ISENSE module is disabled Rev No Item No Date Submitted By Sections Affected Substantial Change s V00 01 19 Jan 2016 Initial version V00 02 15 Feb 2016 Added current sense status register Added write protection bit CSWP and write protection for OCE and OCT V00 03 4 Marc...

Page 394: ...is the non inverting input to the current sense amplifier 15 4 2 AMPM Current Sense Amplifier Inverting Input Pin This pin is the inverting input to the current sense amplifier 15 4 3 AMP Current Sense Amplifier Output Pin This pin is the output of the current sense amplifier At the MCU level this pin is shared with an ADC channel For ADC channel assignment see MCU pin out section AMP AMPP AMPM Co...

Page 395: ...defined at the module level 15 5 2 Register Descriptions This section consists of register descriptions in address order Each description includes a standard register diagram with an associated figure number Details of register bit and field function follow the register diagrams in bit order Unused bits read back zero Address Offset Register Name Bit 7 6 5 4 3 2 1 Bit 0 0x0000 CSEN R CSWP 0 0 0 0 ...

Page 396: ...e protection When set CSWP prevents any further writes to write protected bits Once set CSWP is cleared by reset 0 Write protected bits may be written 1 Write protected bits cannot be written 1 OCE Over Current Comparator Enable This bit enables the over current comparator This bit cannot be modified after CSWP bit is set 0 Over current comparator is disabled 1 Over current comparator is enabled 0...

Page 397: ...ence Manual Rev 1 3 NXP Semiconductors 397 Table 15 3 CSIE Register Field Descriptions Field Description 0 OCIE Over Current Interrupt Enable This bit enables over current interrupt 0 Over current interrupt OCIF is disabled 1 Over current interrupt OCIF is enabled ...

Page 398: ... requested Writing a logic 1 to the bit field clears the flag 0 Current sense amplifier output voltage is less than VOCT 1 Current sense amplifier output voltage is greater than VOCT Module Base 0x0003 Access User read write1 1 Read Anytime Write Never 7 6 5 4 3 2 1 0 R 0 0 0 0 0 0 0 OCSF W Reset 0 0 0 0 0 0 0 0 Unimplemented Figure 15 6 Current Sense Status Register CSSTAT Table 15 5 CSSTAT Regis...

Page 399: ... 7 Current Sense Offset CSOFF Table 15 6 CSOFF Register Field Descriptions Field Description 2 0 OFFS 2 0 Current Sense Amplifier Offset These bits adjust the offset of the current sense amplifier 000 No offset 001 Offset is 3mV 010 Offset is 6mV 011 Offset is 9mV 100 No offset 101 Offset is 9mV 110 Offset is 6mV 111 Offset is 3mV Module Base 0x0005 Access User read write1 1 Read Anytime Write Wri...

Page 400: ... MCU pin out Section The input offset voltage of the current sense amplifier can be adjusted with the OFFS 2 0 bits The output of the current sense amplifier is connected to the positive input of the over current comparator The negative input is Table 15 7 CSOCT Register Field Descriptions Field Description 4 0 OCT 4 0 Over Current Comparator Threshold The over current comparator threshold voltage...

Page 401: ... bit DA converter In order to use the over current comparator OCE and CSE have to be set Figure 15 9 Current Sense Amplifier Connected as Differential Amplifier AMPP Rsense Voffset OFFS 2 0 AMPM AMP Rn a Rn Vref Rp a Rp Vsense Output Voltage to ADC VAMP a Vsense Vref CSE I OCE Voct OCT 4 0 Over Current Condition a Vsense Vref Voct 6 bit DAC ...

Page 402: ...1 MC9S12VRP Family Reference Manual Rev 1 3 402 NXP Semiconductors 15 6 2 Interrupts In case of an over current condition the over current interrupt flag CSIF OCIF asserts This flag generates an interrupt if the enable bit CSIE OCIE is set ...

Page 403: ...own mode 330 k only Current limitation for LIN Bus pin falling edge Overcurrent protection LIN TxD dominant timeout feature monitoring the LPTxD signal Automatic transmitter shutdown in case of an overcurrent or TxD dominant timeout Fulfills the OEM Hardware Requirements for LIN CAN and FlexRay Interfaces in Automotive Applications v1 3 The LIN transmitter is a low side MOSFET with current limitat...

Page 404: ...ity is available Both receiver and transmitter are enabled 3 Receive Only Mode The transmitter is disabled and the receiver is running in full performance mode 4 Standby Mode The transmitter of the LIN Physical Layer is disabled If the wake up feature is enabled the internal pullup resistor can be selected 330 k or 34 k The receiver enters a low power mode and optionally it can pass wake up events...

Page 405: ...2LINPHYV2 MC9S12VRP Family Reference Manual Rev 1 3 NXP Semiconductors 405 Figure 16 1 LIN Physical Layer Block Diagram NOTE The external 220 pF capacitance between LIN and LGND is strongly recommended for correct operation ...

Page 406: ...ter noise 16 2 3 VLINSUP Positive Power Supply External power supply to the chip The VLINSUP supply mapping is described in device level documentation 16 2 4 LPTxD LIN Transmit Pin This pin can be routed to the SCI LPDR1 register bit an external pin or other options Please refer to the PIM chapter of the device specification for the available routing options This input is only used in normal mode ...

Page 407: ...Module Base Address Address Offset where the Module Base Address is defined at the MCU level and the Address Offset is defined at the module level Address Offset Register Name Bit 7 6 5 4 3 2 1 Bit 0 0x0000 LPDR R 0 0 0 0 0 0 LPDR1 LPDR0 W 0x0001 LPCR R 0 0 0 0 LPE RXONLY LPWUE LPPUE W 0x0002 Reserved R Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved W 0x0003 LPSLRM R LPDTD...

Page 408: ...nytime Write Anytime 7 6 5 4 3 2 1 0 R 0 0 0 0 0 0 LPDR1 LPDR0 W Reset 0 0 0 0 0 0 1 1 Unimplemented Figure 16 3 Port LP Data Register LPDR Field Description 1 LPDR1 Port LP Data Bit 1 The LIN Physical Layer LPTxD input see Figure 16 1 can be directly controlled by this register bit The routing of the LPTxD input is done in the Port Inetrgation Module PIM Please refer to the PIM chapter of the dev...

Page 409: ...yer functions are available except that the bus line is held in its recessive state by a high ohmic 330k resistor All registers are normally accessible 1 The LIN Physical Layer is not in shutdown mode 2 RXONLY Receive Only Mode bit This bit controls RXONLY mode 0 The LIN Physical Layer is not in receive only mode 1 The LIN Physical Layer is in receive only mode 1 LPWUE LIN Wake Up Enable This bit ...

Page 410: ... 1 Read Anytime Write Only in special mode 7 6 5 4 3 2 1 0 R Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved W Reset x x x x x x x x Unimplemented Figure 16 5 LIN Test register Table 16 4 Reserved Register Field Description Field Description 7 0 Reserved These reserved bits are used for test purposes Writing to these bits can alter the module functionality Module Base Addre...

Page 411: ...n 16 4 2 for details on how the slew rate control works These bits are only writable in shutdown mode LPE 0 00 Normal Slew Rate optimized for 20 kbit s 01 Slow Slew Rate optimized for 10 4 kbit s 10 Fast Mode Slew Rate up to 250 kbit s This mode is not compliant with the LIN Protocol LIN electrical characteristics like duty cycles reference levels etc are not fulfilled It is only meant to be used ...

Page 412: ...d Figure 16 8 LIN Status Register LPSR Table 16 7 LPSR Field Description Field Description 7 LPDT LIN Transmitter TxD dominant timeout Status Bit This read only bit signals that the LPTxD pin is still dominant after a TxD dominant timeout As long as the LPTxD is dominant after the timeout the LIN transmitter is shut down and the LPTDIF is set again after attempting to clear it 0 If there was a TxD...

Page 413: ...R LPDTIE LPOCIE 0 0 0 0 0 0 W Reset 0 0 0 0 0 0 0 0 Unimplemented Figure 16 9 LIN Interrupt Enable Register LPIE Table 16 8 LPIE Field Description Field Description 7 LPDTIE LIN transmitter TxD dominant timeout Interrupt Enable 0 Interrupt request is disabled 1 Interrupt is requested if LPDTIF bit is set 6 LPOCIE LIN transmitter Overcurrent Interrupt Enable 0 Interrupt request is disabled 1 Interr...

Page 414: ...not allowed if LPDTIF 0 already If the LPTxD is still dominant after clearing the flag the transmitter stays disabled and this flag is set again see 16 4 4 2 TxD dominant timeout Interrupt If interrupt requests are enabled LPDTIE 1 LPDTIF causes an interrupt request 0 No TxD dominant timeout has occurred 1 A TxD dominant timeout has occurred 6 LPOCIF LIN Transmitter Overcurrent Interrupt Flag LPOC...

Page 415: ...LIN Physical Layer can be enabled again NOTE For 20 kbit s and Fast Mode communication speeds the corresponding slew rate MUST be set otherwise the communication is not guaranteed violation of the specified LIN duty cycles For 10 4 kbit s the 20 kbit s slew rate can be set but the EMC performance is worse The up to 250 kbit s slew rate must be chosen ONLY for fast mode not for any of the 10 4 kbit...

Page 416: ...mode 16 4 3 2 Normal Mode The full functionality is available Both receiver and transmitter are enabled The internal pullup resistor can be chosen to be high ohmic 330 k if LPPUE 0 or LIN compliant 34 k if LPPUE 1 If RXONLY is set the module leaves normal mode to enter receive only mode If the MCU enters stop mode the LIN Physical Layer enters standby mode 16 4 3 3 Receive Only Mode Entering this ...

Page 417: ...ed If LPWUE 0 the internal pullup resistor is not selectable and remains at 330 k regardless of the state of the LPPUE bit If LPWUE 1 selecting the 330 k pullup resistor LPPUE 0 reduces the current consumption in standby mode NOTE When using the LIN wake up feature in combination with other non LIN device wake up features like a periodic time interrupt some care must be taken If the device leaves ...

Page 418: ...LIN Physical Layer S12LINPHYV2 MC9S12VRP Family Reference Manual Rev 1 3 418 NXP Semiconductors Figure 16 11 LIN Physical Layer Mode Transitions ...

Page 419: ...the transmitter again the following prerequisites must be met 1 Overcurrent condition is over 2 LPTxD is recessive or the LIN Physical Layer is in shutdown or receive only mode for a minimum of a transmit bit time To re enable the transmitter then the LPOCIF flag must be cleared by writing a 1 NOTE Please make sure that LPOCIF 1 before trying to clear it It is not allowed to try to clear LPOCIF if...

Page 420: ...n tDTLIM the transmitter is disabled and the LPDT status flag and the LPDTIF interrupt flag are set In order to re enable the transmitter again the following prerequisites must be met 1 TxD dominant condition is over LPDT 0 2 LPTxD is recessive or the LIN Physical Layer is in shutdown or receive only mode for a minimum of a transmit bit time To re enable the transmitter then the LPDTIF flag must b...

Page 421: ...nsmitter remains disabled and the LPDTIF flag is set after a time again to indicate that the attempt to re enable has failed This time is equal to minimum 1 IRC period 1 us 2 bus periods maximum 2 IRC periods 2 us 3 bus periods If the bit LPDTIE is set in the LPIE register an interrupt is requested Figure 16 13 shows the different scenarios of TxD dominant timeout interrupt handling Figure 16 13 T...

Page 422: ...ear an error flag always make sure that it is already set 16 5 2 Interrupt handling in Interrupt Service Routine ISR Both interrupts TxD dominant timeout and overcurrent represent a failure in transmission To avoid more disturbances on the transmission line the transmitter is de activated in both cases The interrupt subroutine must take care of clearing the error condition and starting the routine...

Page 423: ...e the interrupts again LPDTIE and LPOCIE 6 Enable the LIN Physical Layer or leave the receive only mode LPCR register 7 Wait for a minimum of a transmit bit before beginning transmission again If there is a problem re enabling the transmitter then the error flag will be set again during step 3 and the ISR will be called again ...

Page 424: ...LIN Physical Layer S12LINPHYV2 MC9S12VRP Family Reference Manual Rev 1 3 424 NXP Semiconductors ...

Page 425: ...n mode The activation of the VSENSE Level Sense Enable BSESE 1 or ADC connection Enable BSEAE 1 closes the path from the VSENSE pin through the resistor chain to ground and enables the associated features if selected The activation of the VSUP Level Sense Enable BSUSE 1 or ADC connection Enable BSUAE 1 closes the path from VSUP pin through the resistor chain to ground and enables the associated fe...

Page 426: ...el Figure 17 1 BATS Block Diagram 17 2 External Signal Description This section lists the name and description of all external ports 17 2 1 VSENSE Supply Battery Voltage Sense Pin This pin can be connected to the supply Battery line for voltage measurements The voltage present at this input is scaled down by an internal voltage divider and can be routed to the internal ADC or to a VSENSE to ADC BV...

Page 427: ... 2 2 VSUP Voltage Supply Pin This pin is the chip supply It can be internally connected for voltage measurement The voltage present at this input is scaled down by an internal voltage divider and can be routed to the internal ADC or to a comparator via an analog multiplexer 17 3 Memory Map and Register Definition This section provides the detailed information of all registers for the BATS module 1...

Page 428: ...andard register diagram with an associated figure number Details of register bit and field function follow the register diagrams in bit order Unused bits read back zero Address Offset Register Name Bit 7 6 5 4 3 2 1 Bit 0 0x0000 BATE R 0 BVHS BVLS 1 0 BSUAE BSUSE BSEAE BSESE W 0x0001 BATSR R 0 0 0 0 0 0 BVHC BVLC W 0x0002 BATIE R 0 0 0 0 0 0 BVHIE BVLIE W 0x0003 BATIF R 0 0 0 0 0 0 BVHIF BVLIF W 0...

Page 429: ...able This bit connects the VSUP pin through the resistor chain to ground and connects the ADC channel to the divided down voltage This bit can be set only if the BSEAE bit is cleared 0 ADC Channel is disconnected 1 ADC Channel is connected 2 BSUSE BATS VSUP Level Sense Enable This bit connects the VSUP pin through the resistor chain to ground and enables the Voltage Level Sense features measuring ...

Page 430: ...ors NOTE When opening the resistors path to ground by changing BSESE BSEAE or BSUSE BSUAE then for a time TEN_UNC two bus cycles the measured value is invalid This is to let internal nodes be charged to correct value BVHIE BVLIE might be cleared for this time period to avoid false interrupts ...

Page 431: ...criptions Field Description 1 BVHC BATS Voltage Sense High Condition Bit This status bit indicates that a high voltage at VSENSE or VSUP depending on selection is present 0 Vmeasured VHBI_A rising edge or Vmeasured VHBI_D falling edge 1 Vmeasured VHBI_A rising edge or Vmeasured VHBI_D falling edge 0 BVLC BATS Voltage Sense Low Condition Bit This status bit indicates that a low voltage at VSENSE or...

Page 432: ...eld Descriptions Field Description 1 BVHIE BATS Interrupt Enable High Enables High Voltage Interrupt 0 No interrupt will be requested whenever BVHIF flag is set 1 Interrupt will be requested whenever BVHIF flag is set 0 BVLIE BATS Interrupt Enable Low Enables Low Voltage Interrupt 0 No interrupt will be requested whenever BVLIF flag is set 1 Interrupt will be requested whenever BVLIF flag is set M...

Page 433: ...n be routed via an internal voltage divider to an internal Analog to Digital Converter Channel Also the BATS module can be configured to generate a low and high voltage interrupt based on VSENSE or VSUP The trigger level of the high and low interrupt are selectable Table 17 5 BATIF Register Field Descriptions Field Description 1 BVHIF BATS Interrupt Flag High Detect The flag is set to 1 when BVHC ...

Page 434: ...To avoid this behavior the software must disable the interrupt generation before disabling the comparator The BATS interrupt vector is named in Table 17 6 Vector addresses and interrupt priorities are defined at MCU level The module internal interrupt sources are combined into one module interrupt signal 17 4 2 1 BATS Voltage Low Condition Interrupt BVLI To use the Voltage Low Interrupt the Level ...

Page 435: ...errupt BVHI To use the Voltage High Interrupt the Level Sensing must be enabled BSESE 1 or BSUSE If measured when a VHBI1 selected with BVHS 0 at selected pin Vmeasure VHBI1_A rising edge or Vmeasure VHBI1_D falling edge or when a VHBI2 selected with BVHS 1 at selected pin Vmeasure VHBI2_A rising edge or Vmeasure VHBI2_D falling edge then BVHC is set BVHC status bit indicates that a high voltage a...

Page 436: ...Supply Voltage Sensor BATSV2 MC9S12VRP Family Reference Manual Rev 1 3 436 NXP Semiconductors ...

Page 437: ...nce Manual Rev 1 3 NXP Semiconductors 437 Chapter 18 64 KByte Flash Module S12FTMRG64K4KV2 Table 18 1 Revision History Revision Number Revision Date Sections Affected Description of Changes V02 00 25 Feb 2016 Initial version ...

Page 438: ...med bit reads 0 It is possible to read from P Flash memory while some commands are executing on D Flash memory It is not possible to read from D Flash memory while a command is executing on P Flash memory Simultaneous P Flash and D Flash operations are discussed in Section 18 4 5 Both P Flash and D Flash memories are implemented with Error Correction Codes ECC that can resolve single bit faults an...

Page 439: ...phrase program operation Ability to read the P Flash memory while programming a word in the D Flash memory Flexible protection scheme to prevent accidental program or erase of P Flash memory 18 1 2 2 D Flash Features 4 Kbytes of D Flash memory composed of one 4 Kbyte Flash block divided into 16 sectors of 256 bytes Single bit fault correction and double bit fault detection within a word during rea...

Page 440: ...8 2 External Signal Description The Flash module contains no signals that connect off chip Bus Clock Divider Clock Command Interrupt Request FCLK Protection Security Registers Flash Interface 16bit internal bus sector 0 sector 1 sector 127 16Kx39 P Flash Error Interrupt Request CPU 2Kx22 sector 0 sector 1 sector 15 D Flash Memory Controller ...

Page 441: ... architecture places the P Flash memory between global addresses 0x3_0000 and 0x3_FFFF as shown in Table 18 3 The P Flash memory map is shown in Figure 18 2 The FPROT register described in Section 18 3 2 9 can be set to protect regions in the Flash memory from accidental program or erase Three separate memory regions one growing upward from global address 0x3_8000 in the Flash memory called the lo...

Page 442: ..._FF07 8 Backdoor Comparison Key Refer to Section 18 4 6 11 Verify Backdoor Access Key Command and Section 18 5 1 Unsecuring the MCU using Backdoor Key Access 0x3_FF08 0x3_FF0B1 1 0x3FF08 0x3_FF0F form a Flash phrase and must be programmed in a single command write sequence Each byte in the 0x3_FF08 0x3_FF0B reserved field should be programmed to 0xFF 4 Reserved 0x3_FF0C1 1 P Flash Protection byte ...

Page 443: ...Lower Region 1 2 4 8 Kbytes 0x3_8000 0x3_9000 0x3_8400 0x3_8800 0x3_A000 P Flash END 0x3_FFFF 0x3_F800 0x3_F000 0x3_E000 Flash Protected Unprotected Higher Region 2 4 8 16 Kbytes Flash Protected Unprotected Region 8 Kbytes up to 29 Kbytes 16 bytes 0x3_FF00 0x3_FF0F Flash Protected Unprotected Region 32 Kbytes P Flash START 0x3_0000 Protection Protection Protection Movable End Fixed End Fixed End ...

Page 444: ...ction 18 4 2 0x0_40B8 0x0_40BF 8 Reserved 0x0_40C0 0x0_40FF 64 Program Once Field Refer to Section 18 4 6 6 Program Once Command Table 18 6 Memory Controller Resource Fields NVMRES1 1 1 NVMRES See Section 18 4 3 for NVMRES NVM Resource detail Global Address Size Bytes Description 0x0_4000 0x0_40FF 256 P Flash IFR see Table 18 5 0x0_4100 0x0_41FF 256 Reserved 0x0_4200 0x0_57FF Reserved 0x0_5800 0x0...

Page 445: ...command execution for more detail see Caution note in Section 18 3 A summary of the Flash module registers is given in Figure 18 4 with detailed descriptions in the following subsections Address Name 7 6 5 4 3 2 1 0 FCLKDIV R FDIVLD FDIVLCK FDIV5 FDIV4 FDIV3 FDIV2 FDIV1 FDIV0 W FSEC R KEYEN1 KEYEN0 RNV5 RNV4 RNV3 RNV2 SEC1 SEC0 W FCCOBIX R 0 0 0 0 0 CCOBIX2 CCOBIX1 CCOBIX0 W Figure 18 4 FTMRG64K4K...

Page 446: ...0 0 0 0 0 DFDIF SFDIF W FPROT R FPOPEN RNV6 FPHDIS FPHS1 FPHS0 FPLDIS FPLS1 FPLS0 W DFPROT R DPOPEN 0 0 0 DPS3 DPS2 DPS1 DPS0 W FCCOBHI R CCOB15 CCOB14 CCOB13 CCOB12 CCOB11 CCOB10 CCOB9 CCOB8 W FCCOBLO R CCOB7 CCOB6 CCOB5 CCOB4 CCOB3 CCOB2 CCOB1 CCOB0 W FRSV1 R 0 0 0 0 0 0 0 0 W FRSV2 R 0 0 0 0 0 0 0 0 W FRSV3 R 0 0 0 0 0 0 0 0 W FRSV4 R 0 0 0 0 0 0 0 0 W FOPT R NV7 NV6 NV5 NV4 NV3 NV2 NV1 NV0 W A...

Page 447: ...t bit 7 remains unwritable CAUTION The FCLKDIV register should never be written while a Flash command is executing CCIF 0 FRSV5 R 0 0 0 0 0 0 0 0 W FRSV6 R 0 0 0 0 0 0 0 0 W FRSV7 R 0 0 0 0 0 0 0 0 W Unimplemented or Reserved 7 6 5 4 3 2 1 0 R FDIVLD FDIVLCK FDIV 5 0 W Reset 0 0 0 0 0 0 0 0 Unimplemented or Reserved Figure 18 5 Flash Clock Divider Register FCLKDIV Table 18 7 FCLKDIV Field Descript...

Page 448: ...se algorithms Table 18 8 shows recommended values for FDIV 5 0 based on the BUSCLK frequency Please refer to Section 18 4 4 Flash Command Operations for more information Table 18 8 FDIV values for various BUSCLK Frequencies BUSCLK Frequency MHz FDIV 5 0 BUSCLK Frequency MHz FDIV 5 0 MIN1 1 BUSCLK is Greater Than this value MAX2 2 BUSCLK is Less Than or Equal to this value MIN1 MAX2 1 0 1 6 0x00 16...

Page 449: ... during reset sequence F1 F1 F1 F1 F1 F1 F1 Unimplemented or Reserved Figure 18 6 Flash Security Register FSEC Table 18 9 FSEC Field Descriptions Field Description 7 6 KEYEN 1 0 Backdoor Key Security Enable Bits The KEYEN 1 0 bits define the enabling of backdoor key access to the Flash module as shown in Table 18 10 5 2 RNV 5 2 Reserved Nonvolatile Bits The RNV bits should remain in the erased sta...

Page 450: ...e not writable 18 3 2 5 Flash Configuration Register FCNFG The FCNFG register enables the Flash command complete interrupt and forces ECC faults on Flash array read access from the CPU 7 6 5 4 3 2 1 0 R 0 0 0 0 0 CCOBIX 2 0 W Reset 0 0 0 0 0 0 0 0 Unimplemented or Reserved Figure 18 7 FCCOB Index Register FCCOBIX Table 18 12 FCCOBIX Field Descriptions Field Description 2 0 CCOBIX 1 0 Common Comman...

Page 451: ...t fault interrupt will not be generated 1 FDFD Force Double Bit Fault Detect The FDFD bit allows the user to simulate a double bit fault during Flash array read operations and check the associated interrupt routine The FDFD bit is cleared by writing a 0 to FDFD 0 Flash array read operations will set the DFDIF flag in the FERSTAT register only if a double bit fault is detected 1 Any Flash array rea...

Page 452: ... detected during the reset sequence see Section 18 6 01 Unimplemented or Reserved Figure 18 11 Flash Status Register FSTAT Table 18 15 FSTAT Field Descriptions Field Description 7 CCIF Command Complete Interrupt Flag The CCIF flag indicates that a Flash command has completed The CCIF flag is cleared by writing a 1 to CCIF to launch a command and CCIF will stay low until command completion or comma...

Page 453: ...block that was under a Flash command operation 1 The DFDIF flag is cleared by writing a 1 to DFDIF Writing a 0 to DFDIF has no effect on DFDIF 2 0 No double bit fault detected 1 Double bit fault detected or a Flash array read operation returning invalid data was attempted while command running 1 The single bit fault and double bit fault flags are mutually exclusive for parity errors an ECC fault o...

Page 454: ...will result in a protection violation error and the FPVIOL bit will be set in the FSTAT register The block erase of a P Flash block is not possible if any of the P Flash sectors contained in the same P Flash block are protected 7 6 5 4 3 2 1 0 R FPOPEN RNV6 FPHDIS FPHS 1 0 FPLDIS FPLS 1 0 W Reset F1 1 Loaded from Flash configuration field during reset sequence F1 F1 F1 F1 F1 F1 F1 Unimplemented or...

Page 455: ...ted area in P Flash memory as shown in Table 18 20 The FPLS bits can only be written to while the FPLDIS bit is set Table 18 18 P Flash Protection Function FPOPEN FPHDIS FPLDIS Function1 1 For range sizes refer to Table 18 19 and Table 18 20 1 1 1 No P Flash Protection 1 1 0 Protected Low Range 1 0 1 Protected High Range 1 0 0 Protected High and Low Ranges 0 1 1 Full P Flash Memory Protected 0 1 0...

Page 456: ... KByte Flash Module S12FTMRG64K4KV2 MC9S12VRP Family Reference Manual Rev 1 3 456 NXP Semiconductors Normal Single Chip Mode while providing as much protection as possible if reprogramming is not required ...

Page 457: ...HS 1 0 FPLS 1 0 3 2 1 0 FPHS 1 0 FPLS 1 0 FPHDIS 1 FPLDIS 1 FPHDIS 1 FPLDIS 0 FPHDIS 0 FPLDIS 1 FPHDIS 0 FPLDIS 0 Scenario Scenario Unprotected region Protected region with size Protected region Protected region with size defined by FPLS defined by FPHS not defined by FPLS FPHS 0x3_8000 0x3_FFFF 0x3_8000 0x3_FFFF FLASH START FLASH START FPOPEN 1 FPOPEN 0 ...

Page 458: ...tion can be added but not removed Writes in Normal Single Chip Mode must increase the DPS value and the DPOPEN bit can only be written from 1 protection disabled to 0 protection enabled If the DPOPEN bit is set the state of the DPS bits is irrelevant All DPOPEN DPS bit registers are writable without restriction in Special Single Chip Mode During the reset sequence fields DPOPEN and DPS of the DFPR...

Page 459: ...ash sectors are protected Table 18 22 DFPROT Field Descriptions Field Description 7 DPOPEN D Flash Protection Control 0 Enables D Flash memory protection from program and erase with protected address range defined by DPS bits 1 Disables D Flash memory protection from program and erase 3 0 DPS 3 0 D Flash Protection Size The DPS 3 0 bits determine the size of the protected area in the D Flash memor...

Page 460: ...register array The generic format for the FCCOB parameter fields in NVM command mode is shown in Table 18 24 The return values are available for reading after the CCIF flag in the FSTAT register has been returned to 1 by the Memory Controller Writes to the unimplemented parameter fields CCOBIX 110 and CCOBIX 111 are ignored with reads from these fields returning 0x0000 Table 18 24 shows the generi...

Page 461: ...read 0 and are not writable 18 3 2 14 Flash Reserved3 Register FRSV3 This Flash register is reserved for factory testing 011 HI Data 1 15 8 LO Data 1 7 0 100 HI Data 2 15 8 LO Data 2 7 0 101 HI Data 3 15 8 LO Data 3 7 0 7 6 5 4 3 2 1 0 R 0 0 0 0 0 0 0 0 W Reset 0 0 0 0 0 0 0 0 Unimplemented or Reserved Figure 18 18 Flash Reserved1 Register FRSV1 7 6 5 4 3 2 1 0 R 0 0 0 0 0 0 0 0 W Reset 0 0 0 0 0 ...

Page 462: ...Flash configuration field at global address 0x3_FF0E located in P Flash memory see Table 18 4 as indicated by reset condition F in Figure 18 22 If a double bit fault is detected while reading the P Flash phrase containing the Flash nonvolatile byte during the reset sequence all bits in the FOPT register will be set 7 6 5 4 3 2 1 0 R 0 0 0 0 0 0 0 0 W Reset 0 0 0 0 0 0 0 0 Unimplemented or Reserved...

Page 463: ... is reserved for factory testing All bits in the FRSV7 register read 0 and are not writable Table 18 25 FOPT Field Descriptions Field Description 7 0 NV 7 0 Nonvolatile Bits The NV 7 0 bits are available as nonvolatile bits Refer to the device user guide for proper use of the NV bits 7 6 5 4 3 2 1 0 R 0 0 0 0 0 0 0 0 W Reset 0 0 0 0 0 0 0 0 Unimplemented or Reserved Figure 18 23 Flash Reserved5 Re...

Page 464: ...01 with both 0b_0000 and 0b_1111 meaning none 18 4 3 Internal NVM resource NVMRES IFR is an internal NVM resource readable by CPU when NVMRES is active The IFR fields are shown in Table 18 5 The NVMRES global address map is shown in Table 18 6 18 4 4 Flash Command Operations Flash command operations are used to modify Flash memory contents The next sections describe How to write the FCLKDIV regist...

Page 465: ... 4 4 2 Command Write Sequence The Memory Controller will launch all valid Flash commands entered using a command write sequence Before launching a command the ACCERR and FPVIOL bits in the FSTAT register must be clear see Section 18 3 2 7 and the CCIF flag should be tested to determine the status of the current command write sequence If CCIF is 0 the previous command write sequence is still active...

Page 466: ...tection Violation Read FSTAT register START Check FCCOB ACCERR FPVIOL Set EXIT Write FCLKDIV register Read FCLKDIV register yes no FDIV Correct no Bit Polling for Command Completion Check yes CCIF Set to identify specific command parameter to load Write to FCCOB register to load required command parameter yes no More Parameters Availability Check Results from previous Command Note FCLKDIV must be ...

Page 467: ...FCMD Command Unsecured Secured NS1 1 Unsecured Normal Single Chip mode SS2 2 Unsecured Special Single Chip mode NS3 3 Secured Normal Single Chip mode SS4 4 Secured Special Single Chip mode 0x01 Erase Verify All Blocks 0x02 Erase Verify Block 0x03 Erase Verify P Flash Section 0x04 Read Once 0x06 Program P Flash 0x07 Program Once 0x08 Erase All Blocks 0x09 Erase Flash Block 0x0A Erase P Flash Sector...

Page 468: ...r in P Flash block that is allowed to be programmed only once 0x08 Erase All Blocks Erase all P Flash and D Flash blocks An erase of all Flash blocks is only possible when the FPLDIS FPHDIS and FPOPEN bits in the FPROT register and the DPOPEN bit in the DFPROT register are set prior to launching the command 0x09 Erase Flash Block Erase a P Flash or D Flash block An erase of the full P Flash block ...

Page 469: ...ommand 0x0B Unsecure Flash Supports a method of releasing MCU security by erasing all D Flash and P Flash blocks and verifying that all D Flash and P Flash blocks are erased 0x0D Set User Margin Level Specifies a user margin read level for the D Flash block 0x0E Set Field Margin Level Specifies a field margin read level for the D Flash block special modes only 0x10 Erase Verify D Flash Section Ver...

Page 470: ...RR or FPVIOL bits are set in the FSTAT register the user must clear these bits before starting any command write sequence see Section 18 3 2 7 CAUTION A Flash word or phrase must be in the erased state before being programmed Cumulative programming of bits within a Flash word or phrase is not allowed 18 4 6 1 Erase Verify All Blocks Command The Erase Verify All Blocks command will verify that all ...

Page 471: ...ash Section command will verify that a section of code in the P Flash memory is erased The Erase Verify P Flash Section command defines the starting point of the code to be verified and the number of phrases Table 18 33 Erase Verify Block Command FCCOB Requirements CCOBIX 2 0 FCCOB Parameters 000 0x02 Flash block selection code 1 0 See Table 18 34 Table 18 34 Flash block selection code description...

Page 472: ...nd FCCOB Requirements CCOBIX 2 0 FCCOB Parameters 000 0x03 Global address 17 16 of a P Flash block 001 Global address 15 0 of the first phrase to be verified 010 Number of phrases to be verified Table 18 37 Erase Verify P Flash Section Command Error Handling Register Error Bit Error Condition FSTAT ACCERR Set if CCOBIX 2 0 010 at command launch Set if command not available in current mode see Tabl...

Page 473: ...earing CCIF to launch the Program P Flash command the Memory Controller will program the data words to the supplied global address and will then proceed to verify the data words read back as expected The CCIF flag will set after the Program P Flash operation has completed Table 18 39 Read Once Command Error Handling Register Error Bit Error Condition FSTAT ACCERR Set if CCOBIX 2 0 001 at command l...

Page 474: ... register accessed by the Program Once command cannot be erased and any attempt to program one of these phrases a second time will not be allowed Valid phrase index values for the Program Once command range from 0x0000 to 0x0007 During execution of the Program Once command any attempt to read addresses within P Flash will return invalid data Table 18 41 Program P Flash Command Error Handling Regis...

Page 475: ...Set if CCOBIX 2 0 101 at command launch Set if command not available in current mode see Table 18 27 Set if an invalid phrase index is supplied Set if the requested phrase has already been programmed1 1 If a Program Once phrase is initially programmed to 0xFFFF_FFFF_FFFF_FFFF the Program Once command will be allowed to execute again on that same phrase FPVIOL None MGSTAT1 Set if any errors have be...

Page 476: ...0 0x09 Global address 17 16 to identify Flash block 001 Global address 15 0 in Flash block to be erased Table 18 47 Erase Flash Block Command Error Handling Register Error Bit Error Condition FSTAT ACCERR Set if CCOBIX 2 0 001 at command launch Set if command not available in current mode see Table 18 27 Set if an invalid global address 17 16 is supplied Set if the supplied P Flash address is not ...

Page 477: ...cess Key command releases security if user supplied keys match those stored in the Flash security bytes of the Flash configuration field see Table 18 49 Erase P Flash Sector Command Error Handling Register Error Bit Error Condition FSTAT ACCERR Set if CCOBIX 2 0 001 at command launch Set if command not available in current mode see Table 18 27 Set if an invalid global address 17 16 is supplied see...

Page 478: ...erify Backdoor Access Key command are aborted set ACCERR until a reset occurs The CCIF flag is set after the Verify Backdoor Access Key operation has completed 18 4 6 12 Set User Margin Level Command The Set User Margin Level command causes the Memory Controller to set the margin level for future read operations of the P Flash or D Flash block Table 18 52 Verify Backdoor Access Key Command FCCOB R...

Page 479: ...r margin levels can be used to check that Flash memory contents have adequate margin for normal level read operations If unexpected results are encountered when checking Flash memory contents at user margin levels a potential loss of information has been detected Table 18 55 Valid Set User Margin Level Settings CCOB CCOBIX 001 Level Description 0x0000 Return to Normal Level 0x0001 User Margin 1 Le...

Page 480: ...nly to the D Flash reads However when the P Flash block is targeted the P Flash field margin levels are applied to both P Flash and D Flash reads It is not possible to apply field margin levels to the P Flash block only Valid margin level settings for the Set Field Margin Level command are defined in Table 18 58 Table 18 57 Set Field Margin Level Command FCCOB Requirements CCOBIX 2 0 FCCOB Paramet...

Page 481: ...r of words Upon clearing CCIF to launch the Erase Verify D Flash Section command the Memory Controller will verify the selected section of D Flash memory is erased The CCIF flag will set after the Erase Verify D Flash Section operation has completed If the section is not erased it means blank check failed both MGSTAT bits will be set Table 18 59 Set Field Margin Level Command Error Handling Regist...

Page 482: ...ck The CCIF flag is set when the operation has completed Table 18 61 Erase Verify D Flash Section Command Error Handling Register Error Bit Error Condition FSTAT ACCERR Set if CCOBIX 2 0 010 at command launch Set if command not available in current mode see Table 18 27 Set if an invalid global address 17 0 is supplied Set if a misaligned word address is supplied global address 0 0 Set if the reque...

Page 483: ...hes the end of the D Flash block FPVIOL Set if the selected area of the D Flash memory is protected MGSTAT1 Set if any errors have been encountered during the verify operation MGSTAT0 Set if any non correctable errors have been encountered during the verify operation Table 18 64 Erase D Flash Sector Command FCCOB Requirements CCOBIX 2 0 FCCOB Parameters 000 0x12 Global address 17 16 to identify D ...

Page 484: ...h error interrupt request For a detailed description of the register bits involved refer to Section 18 3 2 5 Flash Configuration Register FCNFG Section 18 3 2 6 Flash Error Configuration Register FERCNFG Section 18 3 2 7 Flash Status Register FSTAT and Section 18 3 2 8 Flash Error Status Register FERSTAT The logic used for generating the Flash module interrupts is shown in Figure 18 27 Figure 18 2...

Page 485: ...t The following subsections describe these security related subjects Unsecuring the MCU using Backdoor Key Access Unsecuring the MCU in Special Single Chip Mode using BDM Mode and Security Effects on Flash Command Availability 18 5 1 Unsecuring the MCU using Backdoor Key Access The MCU may be unsecured by using the backdoor key access feature which requires knowledge of the contents of the backdoo...

Page 486: ...and the Flash security byte can be reprogrammed to the unsecure state if desired In the unsecure state the user has full control of the contents of the backdoor keys by programming addresses 0x3_FF00 0x3_FF07 in the Flash configuration field 18 5 2 Unsecuring the MCU in Special Single Chip Mode using BDM A secured MCU can be unsecured in Special Single Chip mode by using the following method to er...

Page 487: ...ine reverts to built in default values that leave the module in a fully protected and secured state if errors are encountered during execution of the reset sequence If a double bit fault is detected during the reset sequence both MGSTAT bits in the FSTAT register will be set CCIF is cleared throughout the initialization sequence The Flash module holds off all CPU access for a portion of the initia...

Page 488: ...64 KByte Flash Module S12FTMRG64K4KV2 MC9S12VRP Family Reference Manual Rev 1 3 488 NXP Semiconductors ...

Page 489: ...equency reduced LSDRV over current thresholds updated 0 4 07 Aug 2017 Table A 7 Table A 10 Table B 4 Table E 2 Table F 1 Table F 2 Table F 3 Table G 1 Table H 1 Table H 2 Added temperature options parameters 7a 7c Removed Vddx condition on parameter 7c Swapped range of parameter 13 Updated parameter Added temperature range Added temperature range Removed footnote from parameters 4a and 4b Correcte...

Page 490: ...Figure A 1 shows a 5V GPIO pad driver and the on chip voltage regulator with VDDX output It shows also the power and ground pins VSUP VDDX VSSX and VSSA Px represents any 5V GPIO pin Assume Px is configured as an input The pad driver transistors P1 and N1 are switched off high impedance If the voltage Vin on Px is greater than VDDX a positive injection current Iin will flow through diode D1 into V...

Page 491: ...ctional operation outside these ranges is not guaranteed Stress beyond these limits may affect the reliability or cause permanent damage of the device This device contains circuitry protecting against damage due to high static voltage or electrical fields however it is advised that normal precautions be taken to avoid application of any voltages higher than maximum rated voltages to this high impe...

Page 492: ...A 2 VDDX 0 3 0 3 V 6 Voltage difference VSSX to VSSA VSSX 0 3 0 3 V 7 Digital I O input voltage sources VIN 0 3 6 0 V 8 HVI PL 5 0 input voltage with external resistor REXT_HVI 10k VLx 27 42 V 9 High side driver HS 1 0 VPHS 0 VSUPHS 0 3 V 10 Low side driver LS 2 0 VPLS 0 40 V 11 EXTAL XTAL 3 VILV 0 3 2 16 V 12 TEST input VTEST 0 3 10 V 13 Instantaneous maximum current Single pin limit for all digi...

Page 493: ...imum Input Voltage Limit 7 V Maximum Input Voltage Limit 21 V Table A 5 ESD Protection and Latch up Characteristics Num Rating Symbol Min Max Unit 1 HBM LIN to LGND VHBM 6 kV 2 HBM VSENSE HVI 5 0 to GND 4 kV 3 HBM HS 1 0 to GND 4 kV 4 HBM LS 2 0 to GND 2 kV 5 HBM Pin to Pin all Pins LS 2 0 excluded 2 kV 6 HBM Pin to Pin all Pins LS 2 0 included 1 5 kV 7 CDM Corner Pins VCDM 750 V 8 CDM All other P...

Page 494: ...DA 100 220 nF 3 VDDX Stability capacitor2 3 2 Can be placed anywhere on the 5V supply node VDDA VDDX 3 4 7 F X7R ceramics or 10 F tantalum CVDD5 4 7 or 10 F 4 LIN decoupling capacitor 1 CLIN 220 pF Table A 7 Operating Conditions Num Rating Symbol Min Typ Max Unit 1 Voltage regulator and LINPHY supply voltage1 VSUP VLINSUP 3 5 12 40 V 2 High side driver supply voltage VSUPHS 7 12 401 V 3 Voltage di...

Page 495: ...p single pulse tmax 400ms Operation down to 3 5V is guaranteed without reset however some electrical parameters are specified only in the range above 4 5V 2 The flash program and erase operations must configure fNVMOP as specified in the NVM electrical section 3 Refer to fADCCLK for minimum ADC operating frequency This is derived from the bus clock 4 Please refer to Section A 1 8 Power Dissipation...

Page 496: ...ad is connected between EVDD and ground This power component is included in PINT and is subtracted from overall MCU power dissipation PD PGPIO VI O II O Power dissipation of external load driven by GPIO port Assuming the load is connected between GPIO and ground This power component is included in PINT and is subtracted from overall MCU power dissipation PD Table A 8 Power Dissipation Components P...

Page 497: ...nted board Board meets JESD51 9 specification for 1s or 2s2p board respectively JA 67 C W 4 Thermal resistance 48LQFP double sided PCB with 2 internal planes 200 ft min 1 3 JA 49 C W 5 Junction to Board 48LQFP 4 4 Thermal resistance between the die and the printed circuit board per JEDEC JESD51 8 Board temperature is measured on the top surface of the board near the package JB 34 C W 6 Junction to...

Page 498: ...m allowed combined continuous current PP2 PP1 PP0 IEVDD 30 30 mA 12 Over current Detect Threshold PP2 PP0 IOCD 80 40 mA 13 Internal pull up current All GPIO except RESET VIH min input voltage VIL max IPUL 130 10 A 14 Internal pull up resistance RESET pin RPUL 3 8 5 10 5 K 15 Internal pull down current VIH min input voltage VIL max IPDH 10 130 A 16 Input capacitance Cin 7 pF 17a Injection current3 ...

Page 499: ...meter only applies in stop or pseudo stop mode tP_MASK 3 s 2 Port P L AD interrupt input pulse passed STOP 1 tP_PASS 10 s 3 Port P L AD interrupt input pulse filtered STOP in number of bus clock cycles of period 1 fbus nP_MASK 3 4 Port P L AD interrupt input pulse passed STOP in number of bus clock cycles of period 1 fbus nP_PASS 4 5 IRQ pulse width edge sensitive mode STOP in number of bus clock ...

Page 500: ...7 V V 2 Input Hysteresis VHYS_HVI 250 mV 3 Pin Input Divider Ratio with external series REXT_HVI Ratio VHVI VInternal ADC RatioL_HVI RatioH_HVI 2 6 4 Analog Input Matching Absolute Error on VADC 1 Compared to VHVI RatioL_HVI 1V VHVI 7V Compared to VHVI RatioH_HVI 3V VHVI 21V Direct Mode PTADIRL 1 0 5V VHVI 3 5V 1 Outside of the given VHVI range the error is significant The ratio can be changed if ...

Page 501: ...and Full Stop Current Measurement CPMU REGISTER Bit settings Conditions CPMUSYNR VCOFRQ 1 0 1 SYNDIV 5 0 24 CPMUPOSTDIV POSTDIV 4 0 0 CPMUCLKS PLLSEL 1 CSAD 0 CPMUOSC OSCE 0 Reference clock for PLL is fref firc1m trimmed to 1MHz API settings for STOP current measurement CPMUAPICTL APIEA 0 APIFE 1 APIE 0 CPMUACLKTR trimmed to 10Khz CPMUAPIRH RL set to 0xFFFF Table A 15 Peripheral Configurations for...

Page 502: ...Min Typ Max Unit 1 Run Current ISUPR 15 22 mA 2 Wait Current ISUPW 10 15 mA Table A 17 Stop Current Characteristics Conditions are VSUP 12V Num Rating Symbol Min Typ Max Unit Stop Current all modules off 1 TA TJ 40 C1 1 If MCU is in STOP long enough then TA TJ Die self heating due to stop current can be ignored ISUPS 29 60 A 2 TA TJ 150 C1 ISUPS 140 600 A 3 TA TJ 25 C1 ISUPS 33 65 A 4 TA TJ 85 C1 ...

Page 503: ...out of reset 2 Please note that the core current is derived from VDDX 3 Further limitation may apply due to maximum allowable TJ IDDX 0 0 0 70 25 5 mA mA mA 4 Short Circuit VDDX fall back current VDDX 0 5V IDDX 100 mA 5 Low Voltage Interrupt Assert Level4 Low Voltage Interrupt De assert Level VLVIA VLVID 4 04 4 19 4 23 4 38 4 40 4 49 V V 6a VDDX Low Voltage Reset de assert5 VLVRXD 3 13 V 6b VDDX L...

Page 504: ...the VDDX supply domain only during full performance mode During reduced performance mode stop mode voltage supervision is solely performed by the POR block monitoring core VDD 6 The ACLK trimming must be set that the minimum period equals to 0 2ms 7 CPMUHTTR 0x88 8 This parameter value is subject to change following further characterization Table B 2 Reset and Stop Timing Characteristics Num Chara...

Page 505: ... 7 unless otherwise noted Num Rating Symbol Min Typ Max Unit 1 Nominal crystal or resonator frequency fOSC 4 0 20 MHz 2 Startup Current iOSC 100 A 3a Oscillator start up time 4MHz 1 1 These values apply for carefully designed PCB layouts with capacitors that match the crystal resonator requirements tUPOSC 2 10 ms 3b Oscillator start up time 8MHz 1 tUPOSC 1 6 8 ms 3c Oscillator start up time 16MHz ...

Page 506: ...decreases towards zero for larger number of clock periods N Defining the jitter as The following equation is a good fit for the maximum jitter Figure B 2 Maximum Bus Clock Jitter Approximation NOTE On timers and serial modules a pre scaler will eliminate the effect of the jitter to a large extent 2 3 N 1 N 1 0 tnom tmax1 tmin1 tmaxN tminN J N max 1 t max N N t nom 1 t min N N t nom J N j1 N POSTDI...

Page 507: ...range fVCO 32 50 MHz 3 Reference Clock fREF 1 MHz 4 Lock Detection Lock 0 1 5 1 1 deviation from target frequency 5 Un Lock Detection unl 0 5 2 5 1 6 Time to lock tlock 150 256 fREF s 7 Jitter fit parameter 12 2 fREF 1MHz IRC fBUS 25MHz equivalent fPLL 50MHz CPMUSYNR 0x58 CPMUREFDIV 0x00 CPMUPOSTDIV 0x00 j1 2 8 Jitter fit parameter 13 3 fREF 4MHz XOSCLCP fBUS 24MHz equivalent fPLL 48MHz CPMUSYNR 0...

Page 508: ...t Drivers Switching Port AD output drivers switching can adversely affect the ADC accuracy whilst converting the analog voltage on other port AD pins because the output drivers are supplied from the VDDA VSSA ADC supply pins Although internal design measures are implemented to minimize the affect of output driver noise it Supply voltage 3 13 V VDDA 5 5 V 40o C TJ 150o C Num Rating Symbol Min Typ M...

Page 509: ...llowing points should be considered 1 A current is injected into the channel being converted The channel being stressed has conversion values of 0x3FF in 10 bit mode for analog inputs greater than VRH and 0x000 for values less than VRL unless the current is higher than specified as disruptive condition 2 Current is injected into pins in the neighborhood of the channel being converted A portion of ...

Page 510: ...x input source resistance1 1 1 Refer to Section C 1 1 2 Source Resistance for further information concerning source resistance RS 1 K 2 Total input capacitance Non sampling Total input capacitance Sampling CINN CINS 10 16 pF 3 Input internal Resistance RINA 5 15 k 4 Disruptive analog input current INA 2 5 2 5 mA 5 Coupling ratio positive current injection Kp 1E 4 A A 6 Coupling ratio negative curr...

Page 511: ...Ileakp 0 5 A Ileakn 0 5 A Cbottom 3 7pF S H Cap 6 2pF incl parasitics 920 RINA 9 9K incl parasitics sampling time is 4 to 24 adc clock cycles of 0 25MHz to 8MHz 96 s tsample 500ns Switch resistance depends on input voltage corner ranges are shown Leakage current is guaranteed by specification Complete 10bit conversion takes between 19 and 41 adc clock cycles connected to low ohmic supply during sa...

Page 512: ... 3 1 ADC Accuracy Definitions For the following definitions see also Figure C 2 Differential non linearity DNL is defined as the difference between two adjacent switching steps The integral non linearity INL is defined as the sum of all DNLs DNL i V i V i 1 1LSB 1 INL n DNL i i 1 n V n V 0 1LSB n ...

Page 513: ...n mV 10 15 20 25 30 35 40 85 90 95 100 105 110 115 120 65 70 75 80 60 0 3 2 5 4 7 6 45 3F7 3F9 3F8 3FB 3FA 3FD 3FC 3FE 3FF 3F4 3F6 3F5 8 9 1 2 FF FE FD 3F3 10 Bit Resolution 8 Bit Resolution Ideal Transfer Curve 10 Bit Transfer Curve 8 Bit Transfer Curve 55 10 Bit Absolute Error Boundary 8 Bit Absolute Error Boundary LSB Vi 1 Vi DNL 5000 ...

Page 514: ... conversions 1 ADC values are characterized over the range 4 5 V VDDA 5 5 V Production test uses 4 85 V VDDA 5 15 V Num Rating Symbol Min Typ Max Unit 1 Resolution 10 Bit LSB 5 mV 2 Differential Nonlinearity 10 Bit DNL 1 0 5 1 counts 3 Integral Nonlinearity 10 Bit INL 2 1 2 counts 4 Absolute Error 10 Bit AE 3 2 3 counts 5 Resolution 8 Bit LSB 20 mV 6 Differential Nonlinearity 8 Bit DNL 0 5 0 3 0 5...

Page 515: ...ach HS driver output Note The high side driver is NOT intended to switch capacitive loads A significant capacitive load on HS0 1 would induce a current when the high side driver gate is turned on This current will be sensed by the over current circuitry and eventually lead to an immediate over current shut down In such cases of capacitive loads you can leverage the over current masking feature or ...

Page 516: ...Typ Max Unit 1 High Side Driver Operating Frequency fHS 10 kHz 2 Settling time after the high side driver is enabled set HSEx Bits tHS_settling 1 s 3 Over Current Shutdown Masking Time IRC trimmed to 1 MHz tHSOCM 10 11 s 4 PHS0 1 Rise Time Cload 2 2nF Rload 500 ohm Slew Control off Measuring Condition 10 90 tHSRST 1 5 s 5 High Load Resistance Open Load Detection Switch On Time tHLROLOT 1 s 6 High ...

Page 517: ...aracteristics VLINSUP_LIN 5 51 2 2 12 18 V 2 Current limitation into the LIN pin in dominant state4 for VLIN VLINSUP_LIN_MAX ILIN_LIM 40 200 mA 3 Input leakage current in dominant state driver off internal pull up on VLIN 0V VLINSUP 12V ILIN_PAS_dom 1 mA 4 Input leakage current in recessive state driver off 5V VLINSUP 18V 5V VLIN 18V VLIN VLINSUP ILIN_PAS_rec 20 A 5 Input leakage current when grou...

Page 518: ...RC 3 Propagation delay of receiver trx_pd 6 s 4 Symmetry of receiver propagation delay rising edge w r t falling edge trx_sym 2 2 s LIN PHYSICAL LAYER DRIVER CHARACTERISTICS FOR NOMINAL SLEW RATE 20 0KBIT S 5 Rising falling edge time min to max max to min trise 6 5 s 6 Over current masking window IRC trimmed at 1MHz 40 C TJ 150 C tOCLIM 15 16 s 7 Duty cycle 1 THRec max 0 744 x VLINSUP THDom max 0 ...

Page 519: ...LINSUP 5V the LINPHY is still working but with degraded parametrics 2 For 5V VLINSUP 5 5V characterization showed that all parameters generally stay within the indicated specification except the duty cycles D2 and D4 which may increase and potentially go beyond their maximum limits for highly loaded buses 3 The VLINSUP voltage is provided by the VLINSUP supply This supply mapping is described in d...

Page 520: ...ON 2 3 4 5 4a Output Over Current Threshold The threshold is valid for each LS driver output Note The low side driver is NOT intended to switch capacitive loads A significant capacitive load on LS0 1 would induce a current when the low side driver gate is turned on This current will be sensed by the over current circuitry and eventually lead to an immediate over current shut down ILIMLSX 190 300 4...

Page 521: ...therwise noted Num Ratings Symbol Min Typ Max Unit 1 Low Side Driver Operating Frequency fLS 10 kHz 2 Inductive Load on each LS driver output LPLS 450 mH Table F 3 Static Characteristics LS2DRV LS2 Characteristics noted under conditions 7V VSUP 18 V 40 C TJ 150 C unless otherwise noted Typical values reflect the approximate parameter mean at TA 25 C under nominal conditions unless otherwise noted ...

Page 522: ...mplifier open loop gain AVCSA 100000 4 Current Sense Amplifier common mode rejection ratio CMRRCSA 400 5 Current Sense Amplifier input offset VCSAoff 15 15 mV 6 Max effective Current Sense Amplifier output resistance 0 1V VDDA 0 2V RCSAout 2 8 7a Min Current Sense Amplifier output current 0V VDDA 0 2V 1 1 Output current range for which the effective output resistance specification applies ICSAout ...

Page 523: ...ng edge Deassert Measured on selected pin rising edge Hysteresis measured on selected pin VLBI2_AVLBI2 _D VLBI2_H 6 6 75 0 4 7 25 7 75 V V V 3 Low Voltage Warning LBI 3 Assert Measured on selected pin falling edge Deassert Measured on selected pin rising edge Hysteresis measured on selected pin VLBI3_AVLBI3 _D VLBI3_H 7 7 75 0 4 8 5 9 V V V 4 Low Voltage Warning LBI 4 Assert Measured on selected p...

Page 524: ...cteristics noted under conditions 40 C TJ 150 C unless otherwise noted Typical values reflect the approximate parameter mean at TA 25 C under nominal conditions unless otherwise noted Num Ratings Symbol Min Typ Max Unit 1 Enable Uncertainty Time TEN_UNC 1 s 2 Voltage Warning Low Pass Filter fVWLP_filter 0 5 MHz Characteristics noted under conditions 40 C TJ 150 C unless otherwise noted Typical val...

Page 525: ...its specified as fNVMOP The NVM module does not have any means to monitor the frequency and will not prevent program or erase operation at frequencies above or below the specified minimum When attempting to program or erase the NVM module at a lower frequency a full program or erase transition is not assured All timing parameters are a function of the bus clock frequency fNVMBUS All program and er...

Page 526: ... 80 17 80 17 80 445 00 us 8 Program P Flash 4 Word 164 2925 tPGM_4 0 27 0 28 0 63 11 91 ms 9 Program Once 164 2888 tPGMONCE 0 27 0 28 0 28 3 09 ms 10 Erase All Blocks5 6 100066 19153 tERSALL 96 07 100 84 101 61 163 71 ms 11 Erase Flash Block Pflash 5 100060 17157 tERSBLK_P 95 98 100 75 101 43 159 39 ms 12 Erase Flash Block Dflash 6 100060 2821 tERSBLK_D 95 87 100 64 101 21 153 75 ms 13 Erase P Fla...

Page 527: ...1002 2 Typical data retention values are based on intrinsic capability of the technology measured at high temperature and de rated to 25 C using the Arrhenius equation For additional information on how NXP defines Typical Data Retention please refer to Engineering Bulletin EB618 Years 2 Program Flash number of program erase cycles 40 C Tj 150 C nFLPE 10K 100K3 3 Spec table quotes typical endurance...

Page 528: ...NVM Electrical Parameters MC9S12VRP Family Reference Manual Rev 1 3 528 NXP Semiconductors ...

Page 529: ...MC9S12VRP Family Reference Manual Rev 1 3 NXP Semiconductors 529 Appendix J Package Information ...

Page 530: ...Package Information MC9S12VRP Family Reference Manual Rev 1 3 530 NXP Semiconductors ...

Page 531: ...Package Information MC9S12VRP Family Reference Manual Rev 1 3 NXP Semiconductors 531 ...

Page 532: ...Package Information MC9S12VRP Family Reference Manual Rev 1 3 532 NXP Semiconductors ...

Page 533: ...omer to specify which particular maskset they will receive whereas ordering the generic maskset means that the current preferred maskset which may change over time is shipped In either case the marking on the device will always show the generic mask independent partnumber and the mask set number NOTE Not every combination is offered The mask identifier suffix and the Tape Reel suffix are always bo...

Page 534: ...entifier Suffix First digit s usually references waferfab Last digit usually differentiates mask revision This suffix is omitted in generic partnumbers Memory Size 64 64K Flash 48 48K Flash MCU Family Name Relay based DC motor applications plus extra features Core S12 S12 16 Bit MCU core V indicates part of the MagniV Series Main Memory Type 9 Flash Status Partnumber S or SC Maskset specific partn...

Page 535: ... 0 0 0 0 0 0 0 0 W 0x0008 PORTE R 0 0 0 0 0 0 PTE1 PTE0 W 0x0009 DDRE R 0 0 0 0 0 0 DDRE1 DDRE0 W L 2 0x000A 0x000B Module Mapping Control MMC Map 1 of 2 Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 0x000A Reserved R 0 0 0 0 0 0 0 0 W 0x000B MODE R MODC 0 0 0 0 0 0 0 W L 3 0x000C 0x000D Port Integration Module PIM Map 2 of 4 Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bi...

Page 536: ...it 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 0x0010 Reserved R 0 0 0 0 0 0 0 0 W 0x0011 DIRECT R DP15 DP14 DP13 DP12 DP11 DP10 DP9 DP8 W 0x0012 Reserved R 0 0 0 0 0 0 0 0 W 0x0013 MMCCTL1 R 0 0 0 0 0 0 0 NVMRES W 0x0014 Reserved R 0 0 0 0 0 0 0 0 W 0x0015 PPAGE R 0 0 0 0 PIX3 PIX2 PIX1 PIX0 W 0x0016 Reserved R 0 0 0 0 0 0 0 0 W 0x0017 Reserved R 0 0 0 0 0 0 0 0 W L 6 0x0018 0x0019 Reserved Addre...

Page 537: ...R Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved W L 9 0x0020 0x002F Debug Module S12SDBG Map Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 0x0020 DBGC1 R ARM 0 0 BDM DBGBRK 0 COMRV W TRIG 0x0021 DBGSR R TBF 0 0 0 0 SSF2 SSF1 SSF0 W 0x0022 DBGTCR R 0 TSOURCE 0 0 TRCMOD 0 TALIGN W 0x0023 DBGC2 R 0 0 0 0 0 0 ABCM W 0x0024 DBGTBH R Bit 15 Bit 14 Bit 13 Bit 12 B...

Page 538: ... the contents if the Comparator B or D control register is blended into this address 3 This represents the contents if the Comparator B or D control register is blended into this address L 10 0x0030 0x0033 Reserved Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 0x0030 Reserved R 0 0 0 0 0 0 0 0 W 0x0031 Reserved R 0 0 0 0 0 0 0 0 W 0x0032 Reserved R 0 0 0 0 0 0 0 0 W 0x0033 Reserved ...

Page 539: ...Bit 1 Bit 0 0x0040 TIM0TIOS R Reserved Reserved Reserved Reserved Reserved Reserved IOS1 IOS0 W 0x0041 TIM0CFORC Reserved Reserved Reserved Reserved Reserved Reserved 0 0 FOC1 FOC0 0x0042 0x0043 Reserved R Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved W 0x0044 TIM0TCNTH R Bit 15 14 13 12 11 10 9 Bit 8 W 0x0045 TIM0TCNTL R Bit 7 6 5 4 3 2 1 Bit 0 W 0x0046 TIM0TSCR1 R TEN T...

Page 540: ... Reserved Reserved OCPD1 OCPD0 W 0x006D Reserved R Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved W 0x006E TIM0PTPSR R PTPS7 PTPS6 PTPS5 PTPS4 PTPS3 PTPS2 PTPS1 PTPS0 W 0x006F Reserved R Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved W L 13 0x0070 0x009F Analog to Digital Converter ATD Map Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit ...

Page 541: ...eft Justified Result Data DJM 0 and Section 8 3 2 12 2 Right Justified Result Data DJM 1 W 0x008A ATDDR5 R See Section 8 3 2 12 1 Left Justified Result Data DJM 0 and Section 8 3 2 12 2 Right Justified Result Data DJM 1 W 0x008C ATDDR6 R See Section 8 3 2 12 1 Left Justified Result Data DJM 0 and Section 8 3 2 12 2 Right Justified Result Data DJM 1 W 0x008E ATDDR7 R See Section 8 3 2 12 1 Left Jus...

Page 542: ...B7 PCLKAB6 PCLKAB5 PCLKAB4 PCLKAB3 PCLKAB2 PCLKAB1 PCLKAB0 W 0x00A7 Reserved R 0 0 0 0 0 0 0 0 W 0x00A8 PWMSCLA R Bit 7 6 5 4 3 2 1 Bit 0 W 0x00A9 PWMSCLB R Bit 7 6 5 4 3 2 1 Bit 0 W 0x00AA Reserved R 0 0 0 0 0 0 0 0 W 0x00AB Reserved R 0 0 0 0 0 0 0 0 W 0x00AC PWMCNT0 R Bit 7 6 5 4 3 2 1 Bit 0 W 0 0 0 0 0 0 0 0 0x00AD PWMCNT1 R Bit 7 6 5 4 3 2 1 Bit 0 W 0 0 0 0 0 0 0 0 0x00AE PWMCNT2 R Bit 7 6 5 ...

Page 543: ...MDTY4 R Bit 7 6 5 4 3 2 1 Bit 0 W 0x00C1 PWMDTY5 R Bit 7 6 5 4 3 2 1 Bit 0 W 0x00C2 PWMDTY6 R Bit 7 6 5 4 3 2 1 Bit 0 W 0x00C3 PWMDTY7 R Bit 7 6 5 4 3 2 1 Bit 0 W 0x00C4 0x00C7 Reserved R 0 0 0 0 0 0 0 0 W L 15 0x00C8 0x00CF Serial Communication Interface SCI0 Map Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 0x00C8 SCI0BDH1 R SBR15 SBR14 SBR13 SBR12 SBR11 SBR10 SBR9 SBR8 W 0x00C9 S...

Page 544: ... 0x00CD SCI0SR2 R AMAP 0 0 TXPOL RXPOL BRK13 TXDIR RAF W 0x00CE SCI0DRH R R8 T8 0 0 0 0 0 0 W 0x00CF SCI0DRL R R7 R6 R5 R4 R3 R2 R1 R0 W T7 T6 T5 T4 T3 T2 T1 T0 1 Those registers are accessible if the AMAP bit in the SCI0SR2 register is set to zero 2 Those registers are accessible if the AMAP bit in the SCI0SR2 register is set to one L 15 0x00C8 0x00CF Serial Communication Interface SCI0 Map Addre...

Page 545: ...BERRV BERRIF BKDIF W 0x00D1 SCI1ACR12 R RXEDGIE 0 0 0 0 0 BERRIE BKDIE W 0x00D2 SCI1ACR22 R IREN TNP1 TNP0 0 0 BERRM1 BERRM0 BKDFE W 0x00D3 SCI1CR2 R TIE TCIE RIE ILIE TE RE RWU SBK W 0x00D4 SCI1SR1 R TDRE TC RDRF IDLE OR NF FE PF W 0x00D5 SCI1SR2 R AMAP 0 0 TXPOL RXPOL BRK13 TXDIR RAF W 0x00D6 SCI1DRH R R8 T8 0 0 0 0 0 0 W 0x00D7 SCI1DRL R R7 R6 R5 R4 R3 R2 R1 R0 W T7 T6 T5 T4 T3 T2 T1 T0 L 17 0x...

Page 546: ...8 W 0x010B FCCOBLO R CCOB7 CCOB6 CCOB5 CCOB4 CCOB3 CCOB2 CCOB1 CCOB0 W 0x010C FRSV1 R 0 0 0 0 0 0 0 0 W 0x010D FRSV2 R 0 0 0 0 0 0 0 0 W 0x010E FRSC3 R 0 0 0 0 0 0 0 0 W 0x010F FRSV4 R 0 0 0 0 0 0 0 0 W 0x0110 FOPT R NV7 NV6 NV5 NV4 NV3 NV2 NV1 NV0 W 0x0111 FRSV5 R 0 0 0 0 0 0 0 0 W 0x0112 FRSV6 R 0 0 0 0 0 0 0 0 W 0x0113 FRSV7 R 0 0 0 0 0 0 0 0 W L 18 0x0120 Interrupt Vector Base Register Address...

Page 547: ... 0 0 W 0x0147 HSIF R 0 0 0 0 0 0 HSOCIF1 HSOCIF0 W L 20 0x0150 0x0157 Low Side Drivers LSDRV Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 0x0150 LSDR R 0 0 0 0 0 0 LSDR1 LSDR0 W 0x0151 LSCR R 0 0 0 0 LSOLE1 LSOLE0 LSE1 LSE0 W 0x0152 Reserved R Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved W 0x0153 Reserved R Reserved Reserved Reserved Reserved Reserved Res...

Page 548: ...0 LPDR1 LPDR0 W 0x0161 LPCR R 0 0 0 0 LPE RXONLY LPWUE LPPUE W 0x0162 Reserved R Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved W 0x0163 LPSLRM R LPDTDIS 0 0 0 0 0 LPSLR1 LPSLR0 W 0x0164 Reserved R Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved W 0x0165 LPSR R LPDT 0 0 0 0 0 0 0 W 0x0166 LPIE R LPDTIE LPOCIE 0 0 0 0 0 0 W 0x0167 LPIF R LPDTIF LPOCI...

Page 549: ...0 0 0 0 0 0 0 OCIE W 0x017A CSIF R 0 0 0 0 0 0 0 OCIF W 0x017B CSSTAT R 0 0 0 0 0 0 0 OCSF W 0x017C CSOFF R 0 0 0 0 0 OFFS 2 0 W 0x017D CSOCT R 0 0 0 OCT 4 0 W 0x017E Reserved R 0 0 0 0 0 0 0 0 W 0x017F Reserved R 0 0 0 0 0 0 0 0 W L 24 0x0180 0x01AF Timer Module TIM1 Map Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 0x0180 TIM1TIOS R Reserved Reserved Reserved Reserved Reserved Res...

Page 550: ... W 0x018E TIM1TFLG1 R Reserved Reserved Reserved Reserved Reserved Reserved C1F C0F W 0x018F TIM1TFLG2 R TOF 0 0 0 0 0 0 0 W 0x0190 TIM1TC0H R Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 W 0x0191 TIM1TC0L R Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 W 0x0192 TIM1TC1H R Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 W 0x0193 TIM1TC1L R Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1...

Page 551: ...1 Bit 0 0x0240 PTT R 0 0 0 0 PTT3 PTT2 PTT1 PTT0 W 0x0241 PTIT R 0 0 0 0 PTIT3 PTIT2 PTIT1 PTIT0 W 0x0242 DDRT R 0 0 0 0 DDRT3 DDRT2 DDRT1 DDRT0 W 0x0243 Reserved R 0 0 0 0 0 0 0 0 W 0x0244 PERT R 0 0 0 0 PERT3 PERT2 PERT1 PERT0 W 0x0245 PPST R 0 0 0 0 PPST3 PPST2 PPST1 PPST0 W 0x0246 MODRR0 R 0 0 LS2RR1 LS2RR0 LS1RR1 LS1RR0 LS0RR1 LS0RR0 W 0x0247 MODRR1 R 0 0 PWM5ET1 PWM4ET0 HS1RR1 HS1RR0 HS0RR1 ...

Page 552: ...4 DDRP3 DDRP2 DDRP1 DDRP0 W 0x025B RDRP R 0 0 0 0 0 RDRP2 RDRP1 RDRP0 W 0x025C PERP R 0 0 PERP5 PERP4 PERP3 PERP2 PERP1 PERP0 W 0x025D PPSP R 0 0 PPSP5 PPSP4 PPSP3 PPSP2 PPSP1 PPSP0 W 0x025E PIEP R OCIEP2 OCIEP0 PIEP5 PIEP4 PIEP3 PIEP2 PIEP1 PIEP0 W 0x025F PIFP R OCIFP2 OCIFP0 PIFP5 PIFP4 PIFP3 PIFP2 PIFP1 PIFP0 W 0x0260 Reserved R Reserved Reserved Reserved Reserved Reserved Reserved Reserved Res...

Page 553: ...AD2 PT1AD1 PT1AD0 W 0x0272 Reserved R 0 0 0 0 0 0 0 0 W 0x0273 PTI1AD R 0 0 PTI1AD5 PTI1AD4 PTI1AD3 PTI1AD2 PTI1AD1 PTI1AD0 W 0x0274 Reserved R 0 0 0 0 0 0 0 0 W 0x0275 DDR1AD R 0 0 DDR1AD5 DDR1AD4 DDR1AD3 DDR1AD2 DDR1AD1 DDR1AD0 W 0x0276 0x0278 Reserved R 0 0 0 0 0 0 0 0 W 0x0279 PER1AD R 0 0 PER1AD5 PER1AD4 PER1AD3 PER1AD2 PER1AD1 PER1AD0 W 0x027A Reserved R 0 0 0 0 0 0 0 0 W 0x027B PPS1AD R 0 0...

Page 554: ...CLKTR5 ACLKTR4 ACLKTR3 ACLKTR2 ACLKTR1 ACLKTR0 0 0 W 0x02F4 CPMUAPIRH R APIR15 APIR14 APIR13 APIR12 APIR11 APIR10 APIR9 APIR8 W 0x02F5 CPMUAPIRL R APIR7 APIR6 APIR5 APIR4 APIR3 APIR2 APIR1 APIR0 W 0x02F6 Reserved R 0 0 0 0 0 0 0 0 W 0x02F7 CPMUHTTR R HTOE 0 0 0 HTTR3 HTTR2 HTTR1 HTTR0 W 0x02F8 CPMU IRCTRIMH R TCTRIM 3 0 0 IRCTRIM 9 8 W 0x02F9 CPMU IRCTRIML R IRCTRIM 7 0 W 0x02FA CPMUOSC R OSCE 0 0...

Page 555: ...ess nxp com SalesTermsandConditions NXP the NXP logo NXP SECURE CONNECTIONS FOR A SMARTER WORLD COOLFLUX EMBRACE GREENCHIP HITAG I2C BUS ICODE JCOP LIFE VIBES MIFARE MIFARE CLASSIC MIFARE DESFire MIFARE PLUS MIFARE FLEX MANTIS MIFARE ULTRALIGHT MIFARE4MOBILE MIGLO NTAG ROADLINK SMARTLX SMARTMX STARPLUG TOPFET TRENCHMOS UCODE Freescale the Freescale logo AltiVec C 5 CodeTEST CodeWarrior ColdFire Co...

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