Timer/Pulse-Width Modulator (S08TPMV3)
MC9S08QL8 MCU Series Reference Manual, Rev. 1
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NXP Semiconductors
15.5.2
Description of Reset Operation
Reset clears TPMxSC that disables TPM counter clock and overflow interrupt (TOIE=0). CPWMS,
MSnB, MSnA, ELSnB, and ELSnA are all cleared. This configures all TPM channels for input capture
operation and the associated pins are not controlled by TPM.
15.6
Interrupts
15.6.1
General
The TPM generates an optional interrupt for the main counter overflow and an interrupt for each channel.
The meaning of channel interrupts depends on each channel’s mode of operation. If the channel is
configured for input capture, the interrupt flag is set each time the selected input capture edge is
recognized. If the channel is configured for output compare or PWM modes, the interrupt flag is set each
time the main timer counter matches the value in the 16-bit channel value register.
All TPM interrupts are listed in
The TPM module provides high-true interrupt signals.
15.6.2
Description of Interrupt Operation
For each interrupt source in the TPM, a flag bit is set upon recognition of the interrupt condition such as
timer overflow, channel input capture, or output compare events. This flag is read (polled) by software to
determine that the action has occurred, or an associated enable bit (TOIE or CHnIE) can be set to enable
the interrupt generation. While the interrupt enable bit is set, the interrupt is generated whenever the
associated interrupt flag is set. Software must perform a sequence of steps to clear the interrupt flag before
returning from the interrupt-service routine.
TPM interrupt flags are cleared by a two-step process including a read of the flag bit while it is set followed
by a write of zero to the bit. If a new event is detected between these two steps, the sequence is reset and
the interrupt flag remains set after the second step to avoid the possibility of missing the new event.
Table 15-10. Interrupt Summary
Interrupt
Local
Enable
Source
Description
TOF
TOIE
Counter overflow
Set each time the TPM counter reaches its terminal
count (at transition to its next count value)
CHnF
CHnIE
Channel event
An input capture event or channel match took place
on channel n
Summary of Contents for MC9S08QL4
Page 4: ...MC9S08QL8 MCU Series Reference Manual Rev 1 4 NXP Semiconductors...
Page 36: ...Chapter 3 Modes of Operation MC9S08QL8 MCU Series Reference Manual Rev 1 36 NXP Semiconductors...
Page 56: ...Chapter 4 Memory MC9S08QL8 MCU Series Reference Manual Rev 1 56 NXP Semiconductors...
Page 172: ...Modulo Timer S08MTIMV1 MC9S08QL8 MCU Series Reference Manual Rev 1 172 NXP Semiconductors...
Page 238: ...Development Support MC9S08QL8 MCU Series Reference Manual Rev 1 238 NXP Semiconductors...
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