Interfacing an LCD to the MC9S08LC60, Rev. 0
LCD Module Overview
Freescale Semiconductor
6
Figure 3. LCD Module Clock Tree
2.2.1
External Crystal and the LCD Frame Frequency
The lowest-power configuration for the MC9S08LC60 uses the external clock. It is also advantageous to
select the slowest acceptable clock rate for the LCD base frequency, the LCD frame frequency, and the
LCD charge pump rate that supports the LCD glass in the application. Reducing the clock rate reduces the
current consumption of the LCD module.
2.3
LCD Blinking
One of the most outstanding features of the MC9S08LC60 is the flexible support for segment blinking.
Some features of the segment blinking implementation are:
•
Blink capability is programmable for the entire display or individual segments
•
Multiple programmable options for the blink rate are available
•
Blink functionality is available in stop3 mode
The LCDDRMS bit in the LCDCMD register is used in conjunction with the LCDRAM registers to
provide blinking control for individual segments. If the LCDDRMS bit is cleared, the LCDRAM registers
control the display on/off state for segments on the LCD display. If LCDDRMS bit is set, the LCDRAM
registers control the blink enable on/off state for the corresponding segment. See
,” for example software functions that use the LCDDRMS bit to toggle the LCDRAM
between its function to control the display on/off state and to control blink enable on/off state.
To configure all LCD segments to blink regardless of the contents of the LCDRAM registers while the
LCDDRMS bit is set, the BLKMODE bit in the LCDBCTL control register must also be set.
Internal Clock
External Clock = 32.768 kHz
Source
÷
16
DIV16
÷
(1+CLKADJ[5:0])
CLKADJ[5:0]
LCDCLK
÷
8
÷
(2
LCLK[2:0]
)
LCLK[2:0]
÷
2
LCD Charge Pump Clock
Source
CPCADJ[1:0] LCD Base Frequency
Source
Blink Rate
Source
BRATE[2:0]
÷
2
(1+CPCADJ[1:0])
÷
6
÷
(2
5+BRATE[2:0]
)
÷
2
