INTRODUCTION
1.2 EM LAYOUT
Figure 1-1 shows the layout of the F4EM. Use jumpers J1 and J2 to select the clock source
for the emulator. Jumper header J3 lets you select clock stretching if required. J4 controls the
path of a target reset.
Connector P1 is for a logic analyzer. (Connector P1 has more significance for an EVS system,
as an MMDS05 system includes a bus analyzer). Expansion header connectors P2 and P3
connect the EM and the control board (for an MMDS05) or the EM and the platform board
(for an EVS). Finally, Connectors P4 and P5 allow for connection of a target cable that is
available separately. If you install the F4EM board in the MMDS05, the target cable passes
through a slit in the MMDS05 enclosure.
P3
P2
P1
P5
P4
J1
J2
J3
J4
M68EM05F4
Figure 1-1. HC05F4 Emulator Module
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Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
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