HC05EVS CONFIGURATION AND OPERATION
Table 3-2. Logic Analyzer Connector P4 Signal Descriptions
PIN
MNEMONIC
SIGNAL
1, 3, 4, , 12,
14, 31, 33 —
36, 40
- - - - -
No connection
2, 6
GND
GROUND
5, 7,9,11,13.
15. 17, 19,
21, 23, 25, 27
LA11 — LA0 LATCHED ADDRESSES (bits 11—0) - MCU latched
output address bus.
8,10
LA12,13
LATCHED ADDRESSES (bit 12-13) - MCU latched
output address bus.
16, 18, 20,
22, 24, 26,
28, 30
AD7 — AD0
DATA BUS (bits 7—0) - MCU multiplexed I/O data
bus.
29
LR/W
LATCHED READ/WRITE - Active-high output
signal that indicates the direction of data
transferred on the bus.
32
L I R
LOAD INSTRUCTION REGISTER - Open-drain,
active-low output signal that indicates an
instruction is starting.
37
VCC
+5 VDC POWER - Input voltage (+5 Vdc @ 1.0 A)
used by EVS logic circuits.
38
E
EXTERNAL CLOCK - Internally generated output
clock signal used as a timing reference. The
frequency of E clock is 1/2 the input frequency
of the signal on the OSC2 pin.
39
RESET
RESET - Active-low bidirectional signal for
starting an EVS reset.
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Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
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