NXP Semiconductors LPC84x, User Manual

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UM11029 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2017. All rights reserved.
User manual Rev. 1.0 — 16 June 2017 105 of 515
NXP Semiconductors
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Chapter 8: LPC84x System configuration (SYSCON)
•
The MULT value of the fractional divider is programmed in the FRG0MULT register.
See
Table 152 .
Remark:
To use of the fractional baud rate generator, you must write 0xFF to this register
to yield a denominator value of 256. All other values are not supported.
See also:
Section 17.3.1 “Configure the USART clock and baud rate” .
Section 17.7.1 “Clocking and baud rates” .
8.6.27 Fractional generator 0 multiplier value register
The UART, I
2
C, and SPI clocks come from the FCLK multiplexer. The FRG0CLK is one
clock source of the FCLK multiplexer and its output from the fractional generator 0 can be
adjusted by a fractional divider:
frg0clk = frg0_src_clk/(1 + MULT/DIV).
FRG0_SRC_CLK is input clock of fractional generator 0, which can be the FRO, main
clock, or sys pll clock.
The fractional portion (1 + MULT/DIV) is determined by the two fractional divider registers
in the SYSCON block:
• The DIV denominator of the fractional divider value is programmed in the FRG0DIV
register. See
Table 151 .
•
The MULT value programmed in this register is the numerator of the fractional divider
value used by the fractional rate generator to create the fractional component to the
baud rate.
Remark:
To use of the fractional baud rate generator, you must write 0xFF to this register
to yield a denominator value of 256. All other values are not supported.
See also:
Section 17.3.1 “Configure the USART clock and baud rate” .
Section 17.7.1 “Clocking and baud rates” .
Table 151. Fractional generator 0 divider value register (FRG0DIV, address 0x4004 80D0) bit
description
Bit Symbol Description Reset value
7:0 DIV Denominator of the fractional divider. DIV is equal to the
programmed value +1. Always set to 0xFF to use with the
fractional baud rate generator. 0
31:8 - Reserved -