NXP Semiconductors LPC29 Series, User Manual

Page: 34 / 571

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UM10316_0 © NXP B.V. 2008. All rights reserved.
User manual Rev. 00.06 — 17 December 2008 34 of 571
NXP Semiconductors
UM10316
Chapter 3: LPC29xx Clock Generation Unit (CGU)
5.1 Frequency monitor register
The CGU can report the relative frequency of any operating clock. The clock to be
measured must be selected by software, while the fixed-frequency
BASE_PCR_CLK is
used as the reference frequency. A 14-bit counter then counts the number of cycles of the
measured clock that occur during a user-defined number of reference-clock cycles. When
the MEAS bit is set the measured-clock counter is reset to 0 and counts up, while the 9-bit
reference-clock counter is loaded with the value in RCNT and then counts down towards
0. When either counter reaches its terminal value both counters are disabled and the
MEAS bit is reset to 0. The current values of the counters can then be read out and the
selected frequency obtained by the following equation:
If RCNT is programmed to a value equal to the core clock frequency in kHz and reaches 0
before the FCNT counter saturates, the value stored in FCNT would then show the
measured clock’s frequency in kHz without the need for any further calculation.
Note that the accuracy of this measurement can be affected by several factors.
Quantization error is noticeable if the ratio between the two clocks is large (e.g. 100 kHz
vs. 1kHz), because one counter saturates while the other still has only a small count
Table 14. CGU1 register overview (CGU1 base address: 0xFFFF B000)
Address
offset Access Reset value Name Description Reference
000h R 7100 0011h reserved Reserved -
004h R 0000 0000h reserved Reserved -
008h R 0C00 0000h reserved Reserved -
00Ch R - reserved Reserved -
014h R/W 0000 0000h FREQ_MON Frequency monitor register see Table 3–15
018h R 0000 0FE3h RDET Clock detection register see Table 3–16
01Ch R 0005 1103h PLL_STATUS PLL status register see Table 3–19
020h R/W 0005 1103h PLL_CONTROL PLL control register see Table 3–20
024h R 0000 1001h FDIV_STATUS_0 FDIV 0 frequency-divider status register see Table 3–21
028h R/W 0000 1001h FDIV_CONF_0 FDIV 0 frequency-divider control register see Table 3–22
02Ch R 0000 0000h USB_CLK_STATUS Output-clock status register for
BASE_USB_CLK see Table 3–25
030h R/W 0000 0000h USB_CLK_CONF Output-clock configuration register for
BASE_USB_CLK see Table 3–26
034h R 0000 0000h USB_I2C_CLK_STATU
S Output-clock status register for
BASE_I2C_USB_CLK see Table 3–25
038h R/W 0000 0000h USB_I2C_CLK_CONF Output-clock configuration register for
BASE_I2C_USB_CLK see Table 3–26
03Ch R 0000 0000h OUT_CLK_STATUS Output-clock status register for
BASE_OUT_CLK see Table 3–25
040h R/W 0000 0000h OUT_CLK_CONF Output-clock configuration register for
BASE_OUT_CLK see Table 3–26
FF4h R/W 0000 0000h BUS_DISABLE Bus disable register see Table 3–29
fselected
Qselected
Qref initial
[ ]
Qref final
[ ]
–
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